View UPD75517_144357.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MOS INTEGRATED CIRCUIT
ELECTRON DEVICE
PD75517(A)
4 BIT SINGLE-CHIP MICROCOMPUTER
The PD75517(A) is a 75X series four-bit single-chip microcomputer which enables data processing equivalent to that performed by an eight-bit microcomputer. It is a high-performance product, whose minimum instruction execution time is 0.67 s, shorter than 0.95 s for the conventional PD75516. The ROM and RAM capacities are also larger, and the throughput of the 75X series is further increased. The PD75517(A) is suited to controllers of electric parts of automobiles.
FEATURES
* * * *
Higher reliable than the PD75517 Capacities of program memory, ROM: 24448 x 8 bits Capacity of data memory, RAM: 1024 x 4 bits Function for specifying the instruction execution time (useful for high-speed operation and saving power) * 0.67 s/1.33 s/2.67 s/10.7 s (when the main system clock operates at 6.0 MHz) * 0.95 s/1.91 s/3.82 s/15.3 s (when the main system clock operates at 4.19 MHz) * 122 s (when the subsystem clock operates at 32.768 kHz)
* Built-in A/D converter operable on low voltage
* 8-bit resolution x 8 channels (Successive approximation system) * VDD = 2.7 to 6.0 V
* Many I/O lines: 64 * Enhanced timer function: 4 channels * Built-in 8-bit serial interface: Two channels
* Built-in NEC serial bus interface (SBI)
* Clock operable with ultra-low power consumption (when 5-A TYP. operates on 3 V.) * Product with a built-in PROM available: PD75P518
APPLICATIONS
Controller of electric parts of automobiles
ORDERING INFORMATION
Part number UPD75517GF(A)-xxx-3B9 Remark xxx: Code number Package 80-pin plastic QFP (14 mm x 20 mm) Quality grade Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice. Document No. (O. D. No. Date Published Printed in Japan IC-3183 IC-8683 November 1992 P
NEC CORPORATION 1992
PD75517(A)
FUNCTIONS
Item Built-in memory ROM RAM General registers Instruction cycle 24448 x 8 bits 1024 x 4 bits (4-bit x 8 or 8-bit x 4) x 4 banks * 0.67 s/1.33 s/2.67 s/10.7 s (At 6.0 MHz) * 0.95 s/1.91 s/3.82 s/15.3 s (At 4.19 MHz) * 122 s (At 32.768 kHz) 64 16 (Shared with INT, SIO, PPO, and analog input. Seven lines can be pulled up by software.) 28 (Four lines for LED driving) * 16 lines can be pulled up by software. * Four lines can be pulled down by the mask option. 20 (Eight lines for LED driving. Withstand voltage is 10 V. 20 lines can be pulled up by the mask option.) 8-bit resolution x 8 channels (Successive approximation system) * Capable of low-voltage operation: VDD = 2.7 to 6.0 V Four channels * Timer/event counter * Basic interval timer * Timer/pulse generator (14-bit PWM output enabled) * Clock timer Serial interface Two channels * NEC standard serial bus interface (SBI)/ three-wire SIO: One channel * General clock synchronous serial interface (three-wire SIO): One channel Functions
I/O ports
Total Number of CMOS input lines Number of CMOS I/O lines
Number of N-ch open-drain I/O lines A/D converter
Timer/counter
Interrupt
* Vectored interrupt : Seven sources (External: 3, internal: 4) * Test input : Two sources (External: 1, internal: 1) * Clock test flag is provided. * Parallel edge detection flag for key scan input is provided.
Instruction set
* Set/reset/test/Boolean operation for bit data * 4-bit data transfer, arithmetic/logical, increment/decrement, and comparison instructions * 8-bit data transfer, arithmetic/logical, increment/decrement, and comparison instructions * Ceramic/crystal oscillator for main system clock : 6.0 MHz, 4.19 MHz * Crystal oscillator for subsystem clock : 32.768 kHz VDD = 2.7 to 6.0 V 80-pin plastic QFP (14 x 20 mm)
System clock generator
Operating supply voltage Package
2
PD75517(A)
PIN CONFIGURATION (TOP VIEW)
AN4/P150
AN5/P151
AN6/P152
AN7/P153
P120
P121
P122
P123
P130
P131
P132
AN0 AVREF
Note
1 2 3 4 5 6 7 8
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
P133
AVSS
AN1
AN2
AN3
P140 P141 P142 P143 RESET X2 X1 IC XT2 XT1 VSS P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1 P10/INT0 P11/INT1 P12/INT2 P13/ TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30
VDD VDD P113 P112 P111 P110 P103 P102 P101 P100 P93 P92 P91 P90
PD75517GF(A)-xxx-3B9
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
SI1/P83 SO1/P82 SCK1/P81 PPO/P80 KR7/P73 KR6/P72 KR5/P71 KR4/P70
41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
KR3/P63
KR2/P62
KR1/P61
KR0/P60
P53
P52
P51
P50
VSS
P43
P42
P41
P40
P33
P32
IC: Internally connected. Connect the IC pin to VSS. Note Be sure to supply power to both the VDD pins.
P31
3
4
TI0/P13 PTO0/P20 BUZ/P23 PPO/P80 SI0/SB1/P03 SO0/SB0/P02 SCK0/P01 SI1/P83 SO1/P82 SCK1/P81 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 - KR7/P73 AN0 - AN3 AN4/P150 - AN7/P153 AVREF AVSS
INTERNAL BLOCK DIAGRAM
Basic interval timer INTBT Timer/event counter #0 INTT0 Bank Watch timer Program counter (15) ALU CY SP(8) SBS(2)
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
P00 - P03 P10 - P13 P20 - P23 P30 - P33 P40 - P43 Note P50 - P53 Note P60 - P63 P70 - P73 P80 - P83 P90 - P93 P100 - P103 P110 - P113
INTW General register Timer/pulse generator INTTPG Serial bus interface 0 INTCSI0 Serial interface 1 fX/2N ROM program memory 24448 x 8 bits
Port 6 Port 7 Port 8 Decode and control RAM data memory 1024 x 4 bits Port 9 Port 10 Port 11 Port 12 Port 13 Port 14
P120 - P123 Note P130 - P133 Note P140 - P143 Note P150 - P153
Interrupt control
Clock output control
Clock divider
Clock generator Sub Main
Stand by control
CPU clock
Port 15
Bit seq. buffer (16)
PCL/P22
XT1 XT2 X1 X2
RESET
PD75517(A)
VDD A/D converter
VSS
Note
Port 4, Port 5, Port 12, Port 13, and Port 14 are N-ch open-drain I/O ports with a medium withstand voltage of 10 V.
PD75517(A)
CONTENTS
1.
PIN FUNCTIONS ........................................................................................................................
1.1 1.2 1.3 1.4 1.5 PORT PINS ...................................................................................................................................... NON-PORT PINS ............................................................................................................................ PIN INPUT/OUTPUT CIRCUITS .................................................................................................... CONNECTION OF UNUSED PINS ................................................................................................ SELECTION OF A MASK OPTION ................................................................................................
7
7 9 10 13 14
2.
ARCHITECTURE AND MEMORY MAP OF THE PD75517(A) ..............................................
2.1 2.2 2.3 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................ GENERAL REGISTER BANK CONFIGURATION .......................................................................... MEMORY-MAPPED I/O .................................................................................................................
15
15 19 22
3.
INTERNAL CPU FUNCTIONS ....................................................................................................
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 PROGRAM COUNTER (PC) ........................................................................................................... PROGRAM MEMORY (ROM) ........................................................................................................ DATA MEMORY (RAM) ................................................................................................................. GENERAL REGISTERS ................................................................................................................... ACCUMULATORS .......................................................................................................................... STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) ..................................... PROGRAM STATUS WORD (PSW) .............................................................................................. BANK SELECT REGISTER (BS) .....................................................................................................
27
27 27 29 31 32 32 35 38
4.
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 DIGITAL I/O PORTS ....................................................................................................................... CLOCK GENERATOR ...................................................................................................................... CLOCK OUTPUT CIRCUIT ............................................................................................................. BASIC INTERVAL TIMER ............................................................................................................... CLOCK TIMER ................................................................................................................................. TIMER/EVENT COUNTER ............................................................................................................. TIMER/PULSE GENERATOR ......................................................................................................... SERIAL INTERFACE (CHANNEL 0) ............................................................................................... 4.8.1 4.8.2 4.8.3 4.8.4 4.8.5 4.8.6 4.8.7 Serial Interface (Channel 0) Functions ........................................................................ Configuration of Serial Interface (Channel 0) ............................................................ Register Functions ......................................................................................................... Signals ............................................................................................................................. Serial Interface (Channel 0) Operation ....................................................................... Transfer Start in Each Mode ........................................................................................ Manipulation of SCK0 Pin Output ...............................................................................
39
39 51 60 63 67 69 75 83 84 84 86 94 100 110 111
5
PD75517(A)
4.9 SERIAL INTERFACE (CHANNEL 1) ............................................................................................... 4.9.1 4.9.2 4.9.3 4.9.4 4.10 4.11 Serial Interface (Channel 1) Functions ........................................................................ Serial Interface (Channel 1) Configuration ................................................................. Serial Interface (Channel 1) Operation ....................................................................... 112 112 112 115 117 124
Register Functions ......................................................................................................... 114
A/D CONVERTER ........................................................................................................................... BIT SEQUENTIAL BUFFER ............................................................................................................
5.
INTERRUPT FUNCTION ............................................................................................................ 125
5.1 5.2 5.3 5.4 5.5 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT .................................................... HARDWARE OF THE INTERRUPT CONTROL CIRCUIT .............................................................. MULTIPLE INTERRUPT PROCESSING CONTROL ...................................................................... VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................ 125 127 135 137
INTERRUPT SEQUENCE ................................................................................................................ 134
6.
STANDBY FUNCTION ............................................................................................................... 138
6.1 6.2 6.3 SETTING OF STANDBY MODES AND OPERATION STATUSES ............................................. RELEASE OF THE STANDBY MODES ......................................................................................... OPERATION AFTER A STANDBY MODE IS RELEASED ............................................................ 138 139 141
7. 8.
RESET FUNCTION ..................................................................................................................... 142 INSTRUCTION SET .................................................................................................................... 144
8.1 8.2 8.3
PD75517(A) INSTRUCTIONS ...................................................................................................... 144
INSTRUCTION SET AND ITS OPERATION.................................................................................. INSTRUCTION CODES OF EACH INSTRUCTION ....................................................................... 147 156
9.
ELECTRICAL CHARACTERISTICS ............................................................................................. 162
10. PACKAGE DIMENSIONS ........................................................................................................... 174 11. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 175 APPENDIX A APPENDIX B SERIES PRODUCT FUNCTIONS ............................................................................ 176 DEVELOPMENT TOOLS ......................................................................................... 177
6
PD75517(A)
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
I/ONote 1 circuit type
Pin name
I/O
Also used as INT4 SCK0 SO0/SB0 SI0/SB1
Function
8-bit I/O x
When reset
P00 P01 P02 P03 P10 P11 P12 P13 P20 P21 P22 P23 P30Note 2 P31Note 2 P32Note 2 P33Note 2 P40-P43Note 2
I
4-bit input port (Port 0). For P01 to P03, pull-up resistors can be provided by software in units of 3 bits.
Input
B F-A F-B M-C
I
INT0 INT1 INT2 TI0
With noise elimination function 4-bit input port (Port 1). Pull-up resistors can be provided by software in units of 4 bits. 4-bit I/O port (Port 2). Pull-up resistors can be provided by software in units of 4 bits.
x
Input
B-C
I/O
PTO0 - PCL BUZ
x
Input
E-B
I/O
- - - -
Programmable 4-bit I/O port (Port 3). Input/output can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits.
x
Input
E-C
I/O
-
N-ch open-drain 4-bit I/O port (Port 4). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode.
r
High level (when a pull-up resistor is provided) or high impedance High level (when a pull-up resistor is provided) or high impedance
M
P50-P53Note 2
I/O
-
N-ch open-drain 4-bit I/O port (Port 5). A pull-up resistor can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode.
M
P60 P61 P62 P63 P70 P71 P72 P73
I/O
KR0 KR1 KR2 KR3
Programmable 4-bit I/O port (Port 6). Input/output can be specified bit by bit. Pull-up resistors can be provided by software in units of 4 bits.
r
Input
F-C
I/O
KR4 KR5 KR6 KR7
4-bit I/O port (Port 7). Pull-up resistors can be provided by software in units of 4 bits.
Input
F-A
Notes 1. The circuits enclosed in circles have a Schmitt-triggered input. 2. An LED can be driven directly.
7
PD75517(A)
1.1 PORT PINS (2/2)
I/ONote circuit type E
Pin name P80 P81 P82 P83 P90-P93
I/O
Also used as PPO SCK1 SO1 SI1
Function
8-bit I/O x
When reset
I
4-bit input port (Port 8).
Input
F
E
B
4-bit I/O port (Port 9). A pull-down resistor can be provided bit by bit (mask option). x Low level (when a pull-down resistor is provided) or high impedance Input Input x High level (when a pull-up resistor is provided) or high impedance High level (when a pull-up resistor is provided) or high impedance High level (when a pull-up resistor is provided) or high impedance Input V
I/O
-
P100-P103 P110-P113 P120-P123
I/O I/O I/O
- - -
4-bit I/O port (Port 10) 4-bit I/O port (Port 11) N-ch open-drain, 4-bit I/O port (Port 12). Pull-up resistors can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode.
x
E E M
P130-P133
I/O
-
N-ch open-drain, 4-bit I/O port (Port 13). Pull-up resistors can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode.
x
M
P140-P143
I/O
-
N-ch open-drain, 4-bit I/O port (Port 14). Pull-up resistors can be provided bit by bit (mask option). Withstand voltage is 10 V in open-drain mode.
x
M
P150-P153
I
AN4-AN7 4-bit input port (Port 15)
x
Y-A
Note The circuits enclosed in circles have a Schmitt-triggered input.
8
PD75517(A)
1.2 NON-PORT PINS
I/ONote 1 When reset circuit type - Input Input Input
Pin name
I/O
Also used as P13 P20 P22 P23
Function
TI0 PTO0 PCL BUZ
I O O O
External event pulse input pin for the timer/event counter Timer/event counter output pin Clock output pin Fixed frequency output pin (for buzzer or system clock trimming) Serial clock I/O pin Serial data output pin or serial bus I/O pin Serial data input pin or serial bus I/O pin Edge detection vectored interrupt input pin (Either a rising or falling edge is detected.) Edge detection vectored interrupt input pin (The edge to be detected is selectable.) Edge detection testable input pin (An rising edge is detected.) Synchronous Asynchronous Asynchronous
B-C
E-B E-B E-B
SCK0 SO0/SB0 SI0/SB1 INT4
I/O I/O I/O I
P01 P02 P03 P00
Input Input Input -
F-A F-B M-C B B-C B-C
INT0 INT1 INT2
I
P10 P11
-
I
P12
-
KR0-KR3 KR4-KR7 SCK1 SO1 SI1 AN0-AN3 AN4-AN7 AVREF AVSS X1, X2
I I I/O O I I
P60-P63 P70-P73 P81 P82 P83 - P150-P153
Parallel-falling-edge-sensitive testable input pins Parallel-falling-edge-sensitive testable input pins Serial clock I/O pin Serial data output pin Serial data input pin Analog input pins to A/D converter
Input Input Input Input Input -
F-C F-A F
E
B
Y Y-A
I - I
- - -
A/D converter reference voltage input pin A/D converter reference GND pin Pin for connection to a crystal/ceramic resonator for main system clock generation. When external clock is used, it is input to X1, and its inverted signal is input to X2. Pin for connection to a crystal resonator for subsystem clock generation. When external clock is used, it is input to XT1, and XT2 is left open. System reset input pin Timer/pulse generator pulse output pin Positive power supply pin Ground pin Internally connectedNote 2
- - -
Z - -
XT1 XT2 RESET PPO VDD VSS IC
I - I O - - -
-
-
-
- P80 - - -
- Input - - -
B
E - - -
Notes 1. The circuits enclosed in circles have a Schmitt-triggered input. 2. Be sure to input VSS level to this pin.
9
PD75517(A)
1.3 PIN INPUT/OUTPUT CIRCUITS Fig. 1-1 shows the input/output circuit of each PD75517(A) pin in a simplified manner. Fig. 1-1
Type A VDD Data P-ch IN Output disable N-ch
Pin Input/Output Circuits (1/3)
Type D VDD P-ch OUT
N-ch
CMOS input buffer Type B
Push-pull output which can be set to high-impedance output (off for both P-ch and N-ch) Type E
IN
Data Type D Output disable
IN/OUT
Type A
Schmitt trigger input with hysteresis Type B - C
I/O circuit consisting of a push-pull output of type D and an input buffer of type A Type E - B VDD
VDD P.U.R. P.U.R. enable Data Type D Output disable IN Output disable
P.U.R. P-ch
P-ch
IN/OUT
Type A
P.U.R.: Pull-Up Resistor Schmitt trigger input with hysteresis
P.U.R.: Pull-Up Resistor
10
PD75517(A)
Fig. 1-1 Pin Input/Output Circuits (2/3)
Type E - C VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch Output disable (P-ch) P.U.R. enable VDD P-ch IN/OUT Data Output disable
Type A
Type F - B
VDD P.U.R. P-ch
IN/OUT
N-ch
Output disable (N-ch)
Type B
P.U.R.: Pull-Up Resistor Type F Type F - C
P.U.R.: Pull-Up Resistor VDD P.U.R.
Data Type D Output disable
IN/OUT
P.U.R. enable Data Type D Output disable
P-ch
IN/OUT
Type B
Type B
I/O circuit consisting of a push-pull output of type D and a Schmitt-triggered input of type B Type F - A VDD P.U.R. P.U.R. enable Data Type D Output disable P-ch Data IN/OUT Output disable Type M
P.U.R.: Pull-Up Resistor
VDD P.U.R. (Mask option)
IN/OUT
N-ch (Can sustain +9 V)
Type B
Middle-voltage input buffer (Can sustain + 10 V) P.U.R.: Pull-Up Resistor P.U.R.: Pull-Up Resistor
11
PD75517(A)
Fig. 1-1
Type M - C VDD P.U.R. P.U.R. enable P-ch IN/OUT Data Output disable N-ch IN VDD P-ch N-ch
Pin Input/Output Circuits (3/3)
Type Y - A IN instruction
VDD + Sampling C - AVSS Reference voltage (from voltage tap of serial resistor string)
AVSS
P.U.R.: Pull-Up Resistor Type V Type Z
Input enable
Data Type D Output disable
IN/OUT
AVREF
Type A
P.D.R. (Mask option)
Reference voltage
AVSS P.D.R.: Pull-Down Resistor
Type Y
VDD IN VDD P-ch N-ch + Sampling C -
AVSS AVSS Reference voltage (from voltage tap of serial resistor string) Input enable
12
PD75517(A)
1.4 CONNECTION OF UNUSED PINS Table 1-1
Pin name P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI1/SB1 P10/INT0-P12/INT2 P13/TI0 P20/PTO0 P21 P22/PCL P23/BUZ P30-P33 P40-P43 P50-P53 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80/PPO P81/SCK1 P82/SO1 P83/SI1 P90-P93 P100-P103 P110-P113 P120-P123 P130-P133 P140-P143 P150/AN4-P153/AN7 AN0-AN3 XT1 XT2 AVREF AVSS IC To be connected to VSS or VDD To be left open To be connected to VSS To be connected to VSS Input state : To be connected to VSS or VDD To be connected to VSS or VDD Input state : To be connected to VSS or VDD To be connected to VSS
Recommended Connection of Unused Pins
Recommended connection To be connected to VSS To be connected to VSS or VDD
Output state : To be left open
Output state : To be left open
13
PD75517(A)
1.5 SELECTION OF A MASK OPTION The following mask options are provided for pins. (1) Specification of built-in pull-up and pull-down resistors Table 1-2 Selection of Pull-Up and Pull-Down Resistors
Mask option 1 Pull-up resistors provided (Can be specified bit by bit.) 2 No pull-up resistor provided (Can be specified bit by bit.)
Pin name P40-P43, P50-P53, P120-P123, P130-P133, P140-P143 P90-P93
1
Pull-down resistors provided (Can be specified bit by bit.)
2
No pull-down resistor provided (Can be specified bit by bit.)
(2) Specification of built-in feed-back resistors for subsystem clock oscillation Table 1-3
Pin name XT1, XT2 1
Selection of Feed-Back Resistors
Mask option
2 Feed-back resistors provided (when a subsystem clock is used)
No feed-back resistors provided (when no subsystem clock is used)
Caution Even if built-in feed-back resistors are provided when no subsystem clock is used, operation is not affected except increased power supply current IDD.
14
PD75517(A)
2. ARCHITECTURE AND MEMORY MAP OF THE PD75517(A)
The PD75517(A) has three architectural features: (a) Data memory bank configuration (b) General register bank configuration (c) Memory-mapped I/O Each of these features is explained below. 2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
As shown in Fig. 2-1, the data memory space of the PD75517(A) contains a static RAM (1024 words x 4 bits) at addresses 000H to 3FFH and peripheral hardware (such as I/O ports and timers) at addresses F80H to FFFH. To address a 12-bit address in this data memory space, the PD75517(A) uses such a memory bank configuration that the low-order eight bits are specified with an instruction directly or indirectly, and the highorder four bits are used to specify a memory bank (MB). To specify a memory bank (MB), a memory bank enable flag (MBE) and memory bank select register (MBS) are contained, allowing the addressing indicated in Fig. 2-1 and 2-2 and Table 2-1. (The MBS is a register used to select a memory bank, and can be set to 0, 1, 2, 3, or 15. The MBE is a flag used to determine whether a memory bank selected using the MBS register is to be enabled. The MBE is automatically saved or restored at the time of interrupt processing or subroutine processing, so that it can be freely set in interrupt processing and subroutine processing.) In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and the static RAM in the memory bank specified by the MBS is operated. However, the MBE = 0 mode or the MBE = 1 mode can be selected for each step of program processing for more efficient programming.
Applicable program processing MBE = 0 mode * Interrupt processing * Processing that repeats internal hardware and static RAM operations * Subroutine processing * Usual program processing
MBE = 1 mode
The MBE and MBS are set as indicated below. Example SET1 MBE CLR1 MBE SEL MB0 SEL MB1 SEL MB15 ; MBE 1 ; MBE 0 ; MBS 0 ; MBS 1 ; MBS 15
15
PD75517(A)
Fig. 2-1 Data Memory Organization and Addressing Range of Each Addressing Mode
mem mem.bit MBE =0 MBE =1 @HL @H + mem.bit MBE =0 MBE =1 @DE @DL - Stack pmem. address- fmem.bit @L ing - - -
Addressing mode
Memory bank enable flag 000H 01FH 020H 07FH General resister area Data area Static RAM (memory bank 0)
MBS =0
MBS =0
SBS =0
0FFH 100H
Data area Static RAM (memory bank 1)
MBS =1
MBS =1
SBS =1
1FFH 200H Stack area Data area Static RAM (memory bank 2) MBS =2 MBS =2 SBS =2
2FFH 300H
Data area Static RAM (memory bank 3)
MBS =3
MBS =3
SBS =3
3FFH
Not contained
F80H
FB0H FBFH FC0H FF0H FFFH
Peripheral hardware area (memory bank 15)
MBS = 15
MBS = 15
Remark -- : Don't care
16
PD75517(A)
Table 2-1
Representation format mem.bit
Addressing Modes
Addressing mode 1-bit direct addressing
Specified address Bit specified by bit at the address specified by MB and mem. In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS Address specified by MB and mem. In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS Address specified by MB and mem (mem: even address). In this case: When MBE = 0 and mem = 00H-7FH, MB = 0 When MBE = 0 and mem = 80H-FFH, MB = 15 When MBE = 1, MB = MBS
4-bit direct addressing
mem
8-bit direct addressing
4-bit register indirect addressing
@HL @HL+ @HL- @DE @DL
Address specified by MB and HL. In this case, MB = MBE*MBS
Address specified by DE in memory bank 0 Address specified by DL in memory bank 0 Address specified by MB and HL (with the L register holding an even number). In this case, MB = MBE*MBS Bit specified by bit at the address specified by fmem. In this case: fmem = FB0H-FBFH (interrupt-related hardware) fmem = FF0H-FFFH (I/O port) Bit specified by the low-order 2 bits of the L register at the address specified by the high-order 10 bits of pmem and the high-order 2 bits of the L register. In this case, pmem = FC0H-FFFH
8-bit register indirect addressing Bit manipulation addressing
@HL
fmem.bit
pmem.@L
@H+mem.bit Bit specified by bit at the address specified by MB, H, and the low-order 4 bits of mem. In this case, MB = MBE*MBS Stack addressing -- Address specified by SP in memory bank 0, 1, 2, and 3 selected by SBS
17
PD75517(A)
As summarized in Table 2-1, the PD75517(A) allows both direct and indirect addressing in data memory manipulation for 1-bit data, 4-bit data, and 8-bit data, so that very efficient and simple programming can be performed. Examples 1. The 8-bit data of port 4 and port 5 are transferred to addresses 20H and 21H. CLR1 IN MOV 2. MBE 20H, XA ; MBE 0 ; (21H, 20H) XA XA, PORT4 ; XA Ports 5, 4
When P02 is 0, P33 is set. SKT SET1 PORT0.2 PORT3.3 ; Skip if bit 2 of port 0 is 1 ; Set bit 3 of port 3
3.
A different value is output to port 6, depending on the status of P10. SKF MOV MOV SEL OUT PORT1.0 A, #1010B A, #0101B MB15 PORT6, A ; Skip if bit 0 of port 1 is 0 ; A 1010B (string effect) ; A 0101B (string effect) ; or CLR1 MBE ; Port 6 A Updating Static RAM Addresses
x FH
Fig. 2-2
x 0H 0xH DECS D
DECS D
DECS L
@DL 4-bit transfer
DECS E INCS L DECS DE
@DE 4-bit transfer
INCS E
INCS DE
INCS D Direct addressing Bit manipulation 4-bit 8-bit
INCS D
DECS H
DECS H
Automatic decrement DECS L DECS HL
@HL 4-bit manipulation 8-bit manipulation
Automatic increment INCS L INCS HL
@H + mem.bit Bit manipulation
INCS H FxH
INCS H
18
PD75517(A)
2.2 GENERAL REGISTER BANK CONFIGURATION
The PD75517(A) contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory. (See Fig. 2-3.) To specify a general register bank, a register bank enable flag (RBE) and a register bank select register (RBS) are contained. The RBS is a register used to select a register bank, and the RBE is a flag used to determine whether a register bank selected using the RBS is to be enabled. The register bank (RB) enabled at instruction execution is determined as RB = RBE*RBS As indicated in Table 2-2, the PD75517(A) enables the user to create programs in a very efficient manner by selecting a register bank from the four register banks, depending on whether the processing is normal processing or interrupt processing. (The RBE is automatically saved and set at the time of interrupt processing, and is automatically restored upon completion of interrupt processing.) Table 2-2 Example of the Use of Register Banks with Normal Routines and Interrupt Routines
Use register banks 2 and 3 with RBE = 1. Use register bank 0 with RBE = 0. Use register bank 1 with RBE = 1. (In this case, the RBS needs to be saved and restored.) Save the registers with PUSH or POP.
Normal processing Single interrupt processing Dual interrupt processing
Multiple (triple or more) interrupt processing
The RBE and RBS are set as indicated below. Example SET1 RBE ; RBE 1 CLR1 RBE ; RBE 0 SEL SEL RB0 ; RBS 0 RB3 ; RBS 3
The general registers allow transfers, comparisons, arithmetic/logical operations, and increments and decrements not only on a 4-bit basis, but also on an 8-bit basis with the XA, HL, DE, and BC register pairs. In this case, the register pairs of the register bank that has the inverted value of bit 0 of a register bank specified by RBE*RBS can be specified as XA', HL', DE', and BC', thus providing eight 8-bit registers. (See Fig. 2-4.) Example SET1 SEL MOV RBE RB2 ; RBE 1 ; RBS 2 ; HL HL+XA ; HL' HL'-XA (HL' is HL of register bank 3) ; HL HL+1
XA, #18H ; XA 18H
ADDS HL, XA SUBS HL', XA INCS MOV MOV HL
XA, #00H ; XA 00H (string effect) XA, #10H ; XA 10H (string effect)
19
PD75517(A)
Fig. 2-3 General Register Configuration (4-Bit Processing)
X 01H H 03H D 05H B 07H X 09H H 0BH D 0DH B 0FH X 11H H 13H D 15H B 17H X 19H H 1BH D 1DH B 1FH
A 00H L 02H E 04H C 06H A 08H L 0AH E 0CH C 0EH A 10H L 12H E 14H C 16H A 18H L 1AH E 1CH C 1EH Register bank 3 (RBE*RBS = 3) Register bank 2 (RBE*RBS = 2) Register bank 1 (RBE*RBS = 1) Register bank 0 (RBE*RBS = 0)
20
PD75517(A)
Fig. 2-4 General Register Configuration (8-Bit Processing)
XA 00H HL 02H DE 04H BC 06H XA' 08H HL' 0AH DE' 0CH BC' 0EH When RBE*RBS =0
XA' 00H HL' 02H DE' 04H BC' 06H XA 08H HL 0AH DE 0CH BC 0EH When RBE*RBS =1
XA 10H HL 12H DE 14H BC 16H XA' 18H HL' 1AH DE' 1CH BC' 1EH When RBE*RBS =2
XA' 10H HL' 12H DE' 14H BC' 16H XA 18H HL 1AH DE 1CH BC 1EH When RBE*RBS =3
21
PD75517(A)
2.3 MEMORY-MAPPED I/O
The PD75517(A) employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports to addresses F80H to FFFH in the data memory space as shown in Fig. 2-1. This means that there is no particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.) To manipulate peripheral hardware, the addressing modes listed in Table 2-3 can be used. Table 2-3 Addressing Modes Applicable to Peripheral Hardware
Applicable addressing mode Bit manipulation Direct addressing mode specifying mem.bit with MBE = 0 or (MBE = 1, MBS = 15) Direct addressing mode specifying fmem.bit regardless of MBE and MBS setting Indirect addressing mode specifying pmem.@L regardless of MBE and MBS setting 4-bit manipulation Direct addressing mode specifying mem with MBE = 0 or (MBE = 1, MBS = 15) Register indirect addressing mode specifying @HL with (MBE = 1, MBS = 15) 8-bit manipulation Direct addressing mode specifying mem (even address) with MBE = 0 or (MBE = 1, MBS = 15) Register indirect addressing mode specifying @HL (with the L register containing an even number) with (MBE = 1, MBS = 15)
Applicable hardware All hardware allowing bit manipulation IST0, IST1, MBE, RBE, EOT, IExxx, IRQxxx, PORTn.x BSBn.x PORTn.x All hardware allowing 4-bit manipulation
All hardware allowing 8-bit manipulation addressing
Fig. 2-5 summarizes the I/O map of the PD75517(A). The items in Fig. 2-5 have the following meanings: * Symbol: * R/W : Name representing the address of incorporated hardware, which can be coded in the operand field of an instruction Indicates whether the hardware allows read/write operation. R/W: Both read and write operations possible R W : Read only : Write only
* Number of manipulatable bits: Indicates the number of bits that can be processed in hardware manipulation : Bits can be manipulated on an indicated bit (1-, 4-, or 8-bit) basis. : Particular bits can be manipulated. For these bits, see Remarks.
- : Bits cannot be manipulated on an indicated bit (1-, 4-, or 8-bit) basis.
* Bit manipulation addressing: Bit manipulation addressing applicable in hardware bit manipulation
22
PD75517(A)
Fig. 2-5
PD75517(A) I/O Map (1/4)
Number of bits that can be manipulated
Address b3 F80H
Hardware name (symbol) b2 b1 b0
R/W
1 bit
4 bits
8 bits
Bit manipulation addressing
Remarks Bit 0 is fixed to 0
Stack pointer (SP)
R/W
-
-
F82H F83H
Register bank select register (RBS) Memory bank select register (MBS) Stack bank select register (SBS)
Bank select register (BS) R
-
Note 1
- Bits 3 and 2 are always set to 0. mem.bit Only bit 3 can be manipulated
F84H
R/W
-
-
F85H F86H
Basic interval timer mode register (BTM)
W
-
Basic interval timer (BT)
R
-
-
F90H Timer pulse generator (TPGM) W - F94H Timer/pulse generator modulo register (MODL) F96H Timer/pulse generator modulo register (MODH) R/W - Clock mode register (WM) W - R/W -
- - -
mem.bit
Only bit 3 allows bit manipulation.
-
-
F98H
-
- -
FA0H Timer/event counter 0 mode register (TM0) W - FA2H FA4H Timer/event counter 0 count register (T0) R - TOE0 Note 2 W
- - - -
mem.bit
Only bit 3 can be manipulated
mem.bit
-
FA6H
Timer/event counter 0 modulo register (TMOD0)
W
-
-
Notes 1. 2.
Can be operated separately as the RBS and MBS during 4-bit manipulation. Can also be operated as the BS during 8-bit manipulation. TOE0: Timer/event counter 0 output enable flag (W)
23
PD75517(A)
Fig. 2-5
PD75517(A) I/O Map (2/4)
Number of bits that can be manipulated
Address b3 FB0H IST1
Hardware name (symbol) b2 IST0 b1 MBE b0 RBE
R/W
1 bit R/W R W W W W - -
4 bits
8 bits
Bit manipulation addressing
Remarks
Program status word (PSW)
- fmem.bit Manipulated with EI/DI instruction
FB2H FB3H FB4H
Interrupt priority select register (IPS) Processor clock control register (PCC) INT0 mode register (IM0)
- - - - FB5H INT1 mode resistor (IM1) -
Bit 2 is fixed to 0 Bits 3, 2, and 1 are fixed to 0 Bits 3 and 2 are fixed to 0 Bits 2 and 1 are fixed to 0 -
FB6H
INT2 mode register (IM2)
W
- -
FB7H FB8H FB9H FBAH FBBH FBCH FBDH FBEH FBFH
System clock control register (SCC) IE4 IRQ4 IEBT IRQBT EOT IEW IETPG IET0 IECSI0 IE1 IRQ1 IE0 IE2 IRQW IRQTPG IRQT0 IRQCSI0 IRQ0 IRQ2
W R/W R/W R/W R/W R/W R/W R/W R/W
-
- - fmem.bit -
-
FC0H FC1H FC2H FC3H FC8H
Bit sequential buffer 0 (BSB0) Bit sequential buffer 1 (BSB1) Bit sequential buffer 2 (BSB2) Bit sequential buffer 3 (BSB3) Serial operation mode register 1 (CSIM1)
R/W R/W R/W R/W - W - - mem.bit Only bit 7 allows bit manipulation. mem.bit pmem.@L
CSIE1 FCCH Serial I/O shift register 1 (SIO1) R/W -
-
Remarks 1. IExxx : Interrupt enable flag 2. IRQxxx: Interrupt request flag
24
PD75517(A)
Fig. 2-5
PD75517(A) I/O Map (3/4)
Address b3 FD0H FD8H
Hardware name (symbol) b2 b1 b0
R/W W
Number of bits that can be manipulated
1 bit -
4 bits
8 bits -
Bit manipulation addressing
Remarks
Clock output mode register (CLOM) SOC EOC
- W - - R - - - - -
b3: 1-bit write b2: 1-bit read
A /D conversion mode register (ADM) FDAH SA register (SA) FDCH
Pull-up resistor specification register group A (POGA)
W
-
FE0H
Serial operation mode register 0 (CSIM0) CSIE0 COI WUP CMDD RELD CMDT SBI control register (SBIC) BSYE ACKD ACKE Serial I/O shift register 0 (SIO0)
W R/W RELT R/W ACKT R/W
-
- mem.bit - - mem.bit b6: 1-bit read All bits allow bit manipulation only
FE2H
FE4H
-
-
FE6H Slave address register (SVA) FE8H PM33 PM32 PM31 Port mode register group A (PMGA) PM63 PM62 PM61 - - PM2 Port mode register group B (PMGB) PM7 - PM5 PM11 PM9 PM10 Port mode register group C (PMGC) PM14 - Note PM13 PM30
W
-
-
W PM60 - W PM4 - Note W PM12
-
-
FECH
-
-
FEEH
-
-
Note When developing a program, set 0 to the following two bits of the port mode register group C (PMGC): FEEH, b0 (Equivalent to PM8) FEFH, b3 (Equivalent to PM15) For, while this port on the chip side is used for input only, the corresponding port on the emulator is an I/O port.
25
PD75517(A)
Fig. 2-5
PD75517(A) I/O Map (4/4)
Address b3 FF0H FF1H FF2H FF3H FF4H FF5H FF6H
Note
Hardware name (symbol) b2 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 KR3 Port 6 KR7 Port 7 Port 8 Port 9 Port 10 Port 11 Port 12 Port 13 Port 14 Port 15 KR6 KR2 b1 (PORT0) (PORT1) (PORT2) (PORT3) (PORT4) (PORT5) KR1 (PORT6) KR5 (PORT7) (PORT8) (PORT9) (PORT10) (PORT11) (PORT12) (PORT13) (PORT14) (PORT15) KR4 KR0 b0
R/W R R R/W
Number of bits that can be manipulated
1 bit
4 bits
8 bits -
Bit manipulation addressing
Remerks
- R/W R/W R/W R/W
FF7H Note FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
R/W R R/W R/W - R/W R/W - R/W R/W R -
fmem.bit pmem.@L -
Note
KR0 to KR7 are read-only. In 4-bit parallel input processing, PORT6 or PORT7 is specified.
26
PD75517(A)
3. INTERNAL CPU FUNCTIONS
3.1 PROGRAM COUNTER (PC): 15 BITS
The program counter is a 15-bit binary counter for holding program memory address information. Fig. 3-1 Program Counter Format
PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC
Note that the reset start address must be set within a space of 16K bytes (0000H to 3FFFH). This is because a RESET input sets the low-order six bits of program memory address 0000H in PC13 to PC8, and the contents of address 0001H in PC7 to PC0, and 0 in PC14 for initialization. 3.2 PROGRAM MEMORY (ROM): 24448 WORDS x 8 BITS
The program memory is a mask-programmable ROM with a configuration of 24448 words x 8 bits for storing programs, table data, and so forth. Program memory is addressed by the program counter. Table data can be referenced using the table reference instruction (MOVT). Fig. 3-2 shows the allowable branch address ranges for the branch instructions and subroutine call instructions. The whole-space branch instruction (BRA !addr1) and the whole-space call instruction (CALLA !addr1) allow a direct branch throughout the whole space 0000H-5F7FH. The relative branch instruction (BR $addr) allows a branch to addresses (PC - 15 to PC - 1 and PC + 2 to PC + 16) regardless of block boundaries. The program memory is located at addresses 0000H to 5F7FH containing the following specially assigned addresses. (All areas excluding 0000H and 0001H can be used as normal program memory.) * 0000H to 0001H Vector table for holding the RBE and MBE setting values and program start address at the time of a RESET input. A reset start can be performed at an arbitrary address within a 16K-byte space (0000H to 3FFFH). * 0002H to 000DH Vector table for holding the RBE and MBE setting values and program start address at the time of each vectored interrupt occurrence. Interrupt processing can be started at an arbitrary address within a 16Kbyte space (0000H to 3FFFH). * 0020H to 007FH Table area referenced by the GETI instructionNote Note The GETI instruction can represent an arbitrary 2-byte or 3-byte instruction or two 1-byte instructions in 1 byte, thus reducing the number of program steps. (See Section 8.1.)
27
PD75517(A)
Fig. 3-2
7 0000H MBE 6 RBE Internal reset start address Internal reset start address 0002H MBE RBE INTBT/INT4 start address INTBT/INT4 start address 0004H MBE RBE INT0 start address INT0 start address 0006H MBE RBE INT1 start address INT1 start address 0008H MBE RBE INTCSI0 start address INTCSI0 start address 000AH MBE RBE INTT0 start address INTT0 start address 000CH MBE RBE INTTPG start address INTTPG start address (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) (high-order 6 bits) (low-order 8 bits) Branch/call address specified in GETI insturction GETI instruction reference table 007FH 0080H 07FFH 0800H 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H 3FFFH 4000H 4FFFH 5000H BRCB !caddr instruction branch address 5F7FH BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BR BCDE BR BCXA branch address BRA !addr instruction branch address CALLA !addr instruction branch address BR $addr instruction relative branch address (-15 to -1, +2 to +16) CALL !addr instruction branch address BRCB !caddr instruction branch address BR !addr instruction branch address CALLF !faddr instruction entry address
Program Memory Map
0
0020H
Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address must be set within a 16K-byte space (0000H to 3FFFH). Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with only the low-order 8 bits of the PC changed.
28
PD75517(A)
3.3 DATA MEMORY (RAM)
The data memory is divided into a data area and a peripheral hardware area as shown in Fig. 3-3. The data memory consists of the following memory banks, with each bank made of 256 words x 4 bits: * Memory banks 0, 1, 2, and 3 (data area) * Memory bank 15 (peripheral hardware area) Fig. 3-3 Data Memory Map
Data memory General register area 000H (32 x 4) 01FH 020H 256 x 4 0FFH 100H 0 Memory bank
256 x 4
1
Data area Static RAM (1024 x 4)
Stack area
1FFH 200H
256 x 4
2
2FFH 300H
256 x 4
3
3 FFH Not contained
F80H Peripheral hardware area FFFH 128 x 4 15
29
PD75517(A)
(1) Data area The data area consists of a static RAM, and is used for storing data and as stack memory for subroutine and interrupt execution. The memory can hold data even if CPU operation is stopped in the standby mode, so that it is suitable for holding memory contents with a battery for a long time. The data area can be manipulated with memory manipulation instructions. The static RAM is mapped in memory banks 0, 1, 2, and 3, with each made up of 256 x 4 bits. Bank 0 is used as a data area, but can also be used as a general register area (000H to 01FH). Whole addresses of memory banks 0, 1, 2, and 3 (000H to 3FFH) can be used as a stack area. The static RAM has a configuration of four bits per address. However, use of manipulation instructions enables 1-, 4-, and 8-bit manipulation. Note that an even address must be specified in an 8-bit manipulation instruction. (a) General register area The general register area can be manipulated with either general register manipulation instructions or memory manipulation instructions. Up to 32 4-bit registers are available. Of the 32 general registers, registers not used by the program can be used as a data area or stack area. (b) Stack memory area The stack area can be allocated within a bank with the stack pointer (SP). The bank for the stack area is selected from the memory banks 0, 1, 2, and 3 with the stack bank select register (SBS). Stack area can be used as a save area for subroutine or interrupt execution. Use memory manipulation instructions to manipulate the stack bank select register (SBS) and the stack pointer (SP). (2) Peripheral hardware area The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15. Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the static RAM area. Note that, however, the number of bits to be manipulated at a time varies according to the individual addresses. Addresses to which no peripheral hardware is assigned cannot be accessed since such address locations contain no data memory.
30
PD75517(A)
3.4 GENERAL REGISTERS: 8 x 4 BITS x 4 BANKS
The general registers are mapped to particular addresses in data memory. Four banks of registers are provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A). The register bank (RB) to be enabled at the time of instruction execution is determined by RB = RBE*RBS: (RBS = 0 to 3) Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair for 8-bit manipulation. DL also makes a register pair as well as DE and HL; these three register pairs can be used as data pointers. A general register area can be addressed and accessed as normal RAM, regardless of whether it is used as a register. Fig. 3-4 General Register Format
Data memory Address 000H 001H 002H 003H 004H 005H 006H 007H 008H
***********
Fig. 3-5
3 B 3
Register Pair Format
0 3 C 0 3 E 0 3 L 0 3 A 0 0 0 0
3 A register X register
0
D
L register
3
H register Register bank 0 E register
3
H
D register
X
C register B register
Same as bank 0
Register bank 1
00FH 010H
***********
Same as bank 0
Register bank 2
017H 018H
***********
Same as bank 0
Register bank 3
01FH
31
PD75517(A)
3.5 ACCUMULATORS In the PD75517(A), the A register and the XA register pair function as accumulators. The A register is mainly used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing instructions. For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator. Fig. 3-6 Accumulators
CY
Bit accumulator
A
4-bit accumulator
X
A
8-bit accumulator
3.6
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)
The PD75517(A) uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start address of the stack area is the stack pointer (SP). The stack area is located at addresses 000H to 3FFH in memory banks 0, 1, 2, and 3. Either of the memory banks is selected according to the value of the 2-bit SBS. (See Table 3-1.) Table 3-1 Stack Area to Be Selected by the SBS
SBS SBS1 0 0 1 1
--------------------
SBS2 0 1 0 1
Stack area Memory bank 0 Memory bank 1 Memory bank 2 Memory bank 3
The SP is decremented before a write (save) operation to stack memory, and is incremented after a read (restoration) operation from stack memory. The SBS is set with a 4-bit memory manipulation instruction. Note that the high-order two bits are always set to 00. Fig. 3-8 and 3-9 show data saved to and restored from stack memory in these stack operations. To place the stack area at a given location, the SP can be initialized with an 8-bit memory manipulation instruction, and the SBS can be initialized with a 4-bit memory manipulation instruction. Both can be read from as well. When the SP is initialized to 00H, a stack operation starts at the high-order address (nFFH) of memory bank (n) specified with the SBS. A stack area must be within the memory bank specified with the SBS. If a stack operation exceeds address n00H, the operation returns to address nFFH of the same bank. Stacking beyond memory bank boundaries is enabled only by resetting the SBS. A RESET signal occurrence causes the contents of the SP and the SBS to be undefined, so that the SP must always be initialized to a desired value at the start of the program.
32
PD75517(A)
Fig. 3-7
Address F80H F84H SP7 SP6 SP5 SP4 SP3 0 SP2 0 SP1 SBS1 0 SBS0
Stack Pointer and Stack Bank Select Register Formats
Symbol SP SBS
000H SBS 0FFH 100H Memory bank 1 1FFH 200H Memory bank 2 2FFH 300H Memory bank 3 3FFH SP SP SP Memory bank 0 SP
Example
SP initialization In this example, stack area is allocated in memory bank 2 and stack operation starts at address 2FFH. SEL MB15 ; or CLR1 MBE ; Specify memory bank 2 as a stack area ; SP 00H
MOV A, #2 MOV SBS, A MOV XA, #00H MOV SP, XA
33
PD75517(A)
Fig. 3-8 Data Saved to Stack Memory
PUSH instruction
CALL, CALLA, or CALLF instruction
Interrupt
Stack SP - 6 SP - 5 SP - 2 SP - 1 SP
Lower bits of pair register Upper bits of pair register
Stack PC11 - PC8 0 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 * * * * MBE RBE
Note
Stack SP - 6 SP - 5 SP - 4 SP - 3 SP - 2 SP - 1 SP 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0
SP - 4 SP - 3 SP - 2 SP - 1 SP
*
*
Fig. 3-9
Data Restored from Stack Memory
POP instruction
RET or RETS instruction
RETI instruction
Stack SP SP + 1 SP + 2
Lower bits of pair register Upper bits of pair register
Stack SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 * * 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 * * MBE RBE
Note
Stack SP SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 0 PC11 - PC8 PC14 PC13 PC12 PC3 - PC0 PC7 - PC4 IST1 IST0 MBE RBE PSW CY SK2 SK1 SK0
*
*
Note A PSW other than the MBE or RBE is not saved/restored. Remark Data marked with * is undefined.
34
PD75517(A)
3.7 PROGRAM STATUS WORD (PSW): 8 BITS
The program status word (PSW) consists of various flags closely associated with processor operations. The PSW is mapped to addresses FB0H and FB1H in the data memory space. The four bits at address FB0H can be manipulated with a memory manipulation instruction. Fig. 3-10 Program Status Word Format
Address CY SK2
FB1H SK1 SK0 IST1
FB0H IST0 MBE RBE
Symbol PSW
Cannot be manipulated Can be manipulated by an instruction specifically provided for controlling this flag
Can be manipulated
Table 3-2
PSW Flags Saved/Restored in Stack Operation
Saved/restored flag
Save
When CALL, CALLA, or CALLF instruction is executed When hardware interrupt occurs
MBE and RBE are saved. All PSW bits are saved. MBE and RBE are restored. All PSW bits are restored.
Restore
When RET or RETS instruction is executed When RETI is executed
35
PD75517(A)
(1) Carry flag (CY) The carry flag is a 1-bit flag used to store overflow or underflow occurrence information when an arithmetic operation with a carry (ADDC, SUBC) is executed. The carry flag also has the function of a bit accumulator, and therefore can be used to store the result of a Boolean operation performed on the CY and bit at a specified data memory bit address. The carry flag is manipulated using special instructions, independently of the other PSW bits. A RESET signal occurrence causes the carry flag to be undefined. Table 3-3 Carry Flag Manipulation Instructions
Instruction (mnemonic) Instruction dedicated to carry flag manipulation SET1 CY CLR1 CY NOT1 CY SKT CY MOV1 mem*.bit,CY MOV1 CY,mem*.bit AND1 CY,mem*.bit OR1 CY,mem*.bit XOR1 CY,mem*.bit
Carry flag operation/processing Sets CY to 1. Clears CY to 0. Inverts the contents of CY. Skips if CY is set to 1. Transfers the contents of CY to a specified bit. Transfers the contents of a specified bit to CY. ANDs, ORs, or XORs CY with the contents of a specified bit, then sets the result in CY.
Bit transfer instruction
Bit Boolean instruction
Interrupt handling
Saves CY and all other PSW bits to stack memory in parallel. Interrupt execution ------------------------------------------------------------------Restores CY together with the other PSW bits from stack memory. RETI
Remark
mem*.bit represents the following three addressing modes: * fmem.bit * pmem.@L * @H+mem.bit
Example
Bit 3 at address 3FH is ANDed with P33, then the result is output to P50. MOV MOV1 AND1 MOV1 H, #3H CY, PORT3.3 PORT5.0, CY ; Set high-order 4 bits in register H ; CY CY CY, @H+0FH.3 ; CY Bit 3 at 3FH ; P50 CY
(2) Skip flags (SK2, SK1, SK0) The skip flags are used to store skip status, and are automatically set or reset when the CPU executes an instruction. The user cannot directly manipulate these flags as operands. (3) Interrupt status flag (IST1, IST0) The interrupt status flag is a 2-bit flag used to store the status of processing being performed. (For detailed information, see Table 5-3.)
36
P33
PD75517(A)
Table 3-4 Information Indicated by the Interrupt Status Flag
IST1 0
IST0 0
Status of processing being performed Status 0
Processing and interrupt control Normal program processing is being performed. Any interrupts are acceptable. A lower- or higher-priority interrupt is being serviced. Higher-priority interrupts are acceptable. A higher-priority interrupt is being serviced. No interrupts are acceptable. Not to be set
0
1
Status 1
1
0
Status 2
1
1
--
The interrupt priority control circuit (see Fig. 5-1) checks this flag to control multiple interrupts. The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted, then are automatically set to a one-step higher status. The RETI instruction restores the contents present before an interrupt occurs. The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of processing being performed can be changed by program control. Caution The user must always disable interrupts with the DI instruction before manipulating this flag, and must enable interrupts with the EI instruction after manipulating this flag. (4) Memory bank enable flag (MBE) The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for the high-order four bits of a 12-bit data memory address. When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space to be addressed. When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See Fig. 2-1.) A RESET signal occurrence automatically initializes the MBE by setting the MBE to the content of bit 7 at program memory address 0. In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address table for servicing the interrupt. Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used. (5) Register bank enable flag (RBE) The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank configuration. When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending on the setting of the register bank select register (RBS). When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting of the RBS. A RESET signal occurrence automatically initializes the RBE by setting the RBE to the content of bit 6 at program memory address 0. When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.
37
PD75517(A)
3.8 BANK SELECT REGISTER (BS)
The bank select register consists of a register bank select register (RBS) and memory bank select register (MBS), which specify a register bank and memory bank to be used, respectively. The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively. The contents of BS can be saved to or restored from a stack area eight bits at a time by using the PUSH BS/POP BS instruction. Fig. 3-11
Address F83H MBS MBS3 MBS2 MBS1 MBS0 0 0
Bank Select Register Format
F82H RBS RBS1 RBS0
Symbol BS
(1) Memory bank select register (MBS) The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data memory address. The contents of this register specify a memory bank to be accessed. Note, however, that the PD75517(A) allows only memory banks 0, 1, 2, 3, and 15 to be specified. The MBS is set with the SEL MBn instruction (n = 0, 1, 2, 3, 15) Fig. 2-1 shows the range of addressing using MBE and MBS settings. A RESET signal occurrence initializes the MBS to 0. (2) Register bank select register (RBS) The register bank select register specifies a register bank to be used as general registers; a register bank can be selected from register banks 0 to 3. The RBS is set with the SEL RBn instruction (n = 0 to 3). A RESET signal occurrence initializes the RBS to 0. Table 3-5 Register Bank to Be Selected with the RBE and RBS
RBS RBE 0 3 0 2 0 1 x 0 0 1 0 0 1 1 0 1 Bank 2 is selected. Bank 3 is selected. 0 x 0 1 Register bank Bank 0 is always selected. Bank 0 is selected. Bank 1 is selected.
Always 0
Remark
x: Don't care
38
PD75517(A)
4. PERIPHERAL HARDWARE FUNCTIONS
4.1 DIGITAL I/O PORTS The PD75517(A) employs memory-mapped I/O, enabling all I/O ports to be mapped to data memory space. Fig. 4-1 Data Memory Address Assigned to Digital Port
3 P03 P13 P23 P33 P43 P53 P63 P73 P83 P93 P103 P113 P123 P133 P143 P153 2 P02 P12 P22 P32 P42 P52 P62 P72 P82 P92 P102 P112 P122 P132 P142 P152 1 P01 P11 P21 P31 P41 P51 P61 P71 P81 P91 P101 P111 P121 P131 P141 P151 0 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 P100 P110 P120 P130 P140 P150 Symbol PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 PORT 9 PORT 10 PORT 11 PORT 12 PORT 13 PORT 14 PORT 15
Address FF0H FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H FFAH FFBH FFCH FFDH FFEH FFFH
Table 4-1 lists the I/O port manipulation instructions. These instructions provide a wide range of control including 8-bit I/O and bit manipulation as well as 4-bit I/O. Examples 1. Test the state of P13, then output different values to ports 4 and 5 according to the test result. SKT PORT1.3 ; Skip if bit 3 of port 1 is 1 ; XA 14H

MOV XA, #18H MOV XA, #14H SEL MB15
; XA 18H
Consecutive
; or CLR1 MBE
OUT PORT4, XA ; Ports 5 and 4 XA 2. SET1 PORT4.@L ; Set the bit of ports 4 to 7 specified by the L register to 1
39
PD75517(A)
Table 4-1 I/O Pin Manipulation Instructions
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IN IN A, PORTnNote 1 XA, PORTnNote 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- r r r r r r r r r r r r r -- -- -- -- r r r r r r r r -- -- r r -- -- r -- -- -- -- r -- -- -- r r r r r -- -- r -- -- -- -- -- -- -- -- --
OUT OUT
PORTn.ANote 1 PORTn.XANote 1
SET1 PORTn.bit SET1 PORTn.@LNote 2
CLR1 PORTn.bit CLR1 PORTn.@LNote 2
SKT PORTn.bit SKT PORTn.@LNote 2
SKF PORTn.bit SKF PORTn.@LNote 2
MOV1 CY, PORTn.bit MOV1 CY, PORTn.@LNote 2
MOV1 PORTn.bit, CY MOV1 PORTn.@L, CYNote 2
AND1 CY, PORTn.bit AND1 CY, PORTn.@LNote 2
OR1 CY, PORTn.bit OR1 CY, PORTn.@LNote 2
XOR1 CY, PORTn.bit XOR1 CY, PORTn.@LNote 2
Notes 1. Before an instruction is executed, MBE must be set to 0, or MBS must be set to 15 when MBE is 1. 2. The lower 2 bits of an address and a bit address are specified indirectly with the L register.
40
PD75517(A)
(1) Types, features, and configurations of digital I/O ports Table 4-2 lists the types of digital I/O ports. Fig. 4-2 through 4-8 present the configurations of the ports. Table 4-2
Port name PORT0 Function 4-bit input
Types and Features of Digital Ports
Operation and feature Remarks
Allows read and test at any time regardless of Also used as INT4, SCK0, SO0/ the operation modes of dual function pins. SB0, and SI0/SB1. Also used as INT0 to INT2, and TI0.
PORT1
PORT2 PORT3Note PORT4Note PORT5Note PORT6
4-bit I/O
Allows input or output mode setting in units Also used as PTO0, PCL, and BUZ. of 4 bits. Allows input or output mode setting in units -- of 1 or 4 bits.
4-bit I/O (N-chan- Allows input or output Ports 4 and 5 may be The use of pull-up resistors can nel open-drain 10 V) mode setting in units paired, allowing data be specified by mask options in of 4 bits. I/O in units of 8 bits. units of bits. 4-bit I/O Allows input or output Ports 6 and 7 may be Also used as KR0 to KR3. mode setting in units paired, allowing data of 1 or 4 bits. I/O in units of 8 bits. Allows input or output mode setting in units of 4 bits. 4-bit input Also used as KR4 to KR7.
PORT7
PORT8
Allows read and test at any time regardless of Also used as PPO, SCK1, SO1, the operation modes of dual function pins. and SI1. Allows input or output mode setting in units The use of a pull-down resistor of 4 bits. can be specified by a mask option in units of bits. Allows input or output mode setting in units of 4 bits. --
PORT9
4-bit I/O
PORT10 PORT11 PORT12 PORT13 PORT14 PORT15
4-bit I/O
4-bit I/O (N-chan- Allows input or output mode setting in units The use of pull-up resistors can be specified by mask options in nel open-drain 10 V) of 4 bits. units of bits. 4-bit input Allows read and test at any time regardless of Also used as AN4 to AN7. the operation modes of dual function pins.
Note This port can directly drive the LED. P10 is also used as an external vectored interrupt input pin. This input is provided with a noise eliminator. (See Section 5.2 for details.) The use of pull-up resistors can be specified for ports 0 (excluding pin P00/INT4), 1 to 3, 6, and 7 by software.
41
PD75517(A)
(2) Setting the I/O mode As shown in Fig. 4-9, the I/O mode for each I/O port is set with the port mode register. Each port functions as an input port when the corresponding bit of the port mode register is set to 0, and functions as an output port when the same bit is set to 1. An 8-bit memory manipulation instruction is used to set port mode register group A, B, or C. The generation of a RESET signal clears all the bits of each port mode register to 0. This means that the output buffers are set off and all ports function in the input mode.
42
PD75517(A)
Fig. 4-2
SI0
Configuration of Ports 0, 1, and 8
SO0 P01 output latch Internal SCK0 VDD
SCK0 INT4
Selector 8 CSIM0
Selector
Pull-up resistor P-ch Bit 0 of POGA P00/INT4 P01/SCK0 P02/SO0/SB0 P03/SI0/SB1
Input buffer
Output buffer which can be switched to either push-pull output or N-ch open-drain output Pull-up resistor
VDD
Internal bus
P-ch Bit 1 of POGA Input buffer or fX/64 Noise elimination circuit P10/INT0 P11/INT1 P12/INT2 P13/ TI0 TI0 INT2 INT1 INT0 Input buffer with hysteresis
SI1
SO1 SCK1
Internal SCK1
PPO
8
CSIM1
P80/PPO P81/SCK1 P82/SO1 P83/SI1 Input buffer
43
PD75517(A)
Fig. 4-3 Configuration of Ports 3n and 6n (n = 0 to 3)
VDD Input buffer MPX PMmn = 1 Bit m of POGA
Internal bus
PMmn = 0
Pull-up resistor
P-ch
Output buffer Output latch Pmn
PMmn Bit of port mode register group A m = 3, 6 n = 0 to 3
Fig. 4-4
Configuration of Ports 2 and 7
VDD
Pull-up resistor P-ch Bit m of POGA Input buffer PMm = 0
MPX
PMm = 1
Internal bus
Pm0 Pm1 Pm2 Pm3 Output buffer PMm Bit of port mode register group B or C (m = 2, 7)
Output latch
44
PD75517(A)
Fig. 4-5 Configuration of Ports 4, 5, 12, 13, and 14
VDD Pull-up resistor (mask option) Input buffer PMm = 0
MPX
PMm = 1
Internal bus
Pm0 Pm1 Pm2 Pm3 Open-drain output buffer
Output latch
PMm
Port mode registers Bit of the group B (m = 4, 5): Ports 4 and 5 Bit of the group C (m = 4, 5, 6): Ports 12, 13, and 14
45
PD75517(A)
Fig. 4-6
Bit 1 of port mode register group C PM9
Configuration of Port 9
Output buffer P90 P91 P92 P93
Output latch
Internal bus
Input buffer
MPX
PM9 = 1
PM9 = 0
Pull-down resistors (mask option)
46
PD75517(A)
Fig. 4-7 Configuration of Ports 10 and 11
Input buffer PMm = 0
MPX
PMm = 1
Internal bus
Pm0 Pm1 Pm2 Pm3 CMOS output buffer PMm Bit of port mode register group C (m = 10, 11)
Output latch
Fig. 4-8
Input instruction
Configuration of Port 15
Input buffer AN4/P150
Internal bus
AN5/P151
AN6/P152
AN7/P153
To A /D converter
47
PD75517(A)
Fig. 4-9 (a) Port mode register group A
Address FE8H 7 6 5 4 3 2 1 0 Symbol PMGA P30 I/O specification P31 I/O specification P32 I/O specification P33 I/O specification P60 I/O specification P61 I/O specification P62 I/O specification P63 I/O specification
Formats of Port Mode Registers
PM63 PM62 PM61 PM60 PM33 PM32 PM31 PM30
(b) Port mode register group B
Address FECH 7 PM7 6 -- 5 PM5 4 PM4 3 -- 2 PM2 1 -- 0 -- Symbol PMGB Port 2 (P20-P23) I/O specification Port 4 (P40-P43) I/O specification Port 5 (P50-P53) I/O specification Port 7 (P70-P73) I/O specification
(c) Port mode register group C
Address FEEH 7 6 5 4 3 2 1 PM9 0 --Note Symbol PMGC Port 9 (P90 - P93) I/O specification Port 10 (P100 - P103) I/O specification Port 11 (P110 - P113) I/O specification Port 12 (P120 - P123) I/O specification Port 13 (P130 - P133) I/O specification Port 14 (P140 - P143) I/O specification Contents of specification 0 1 Input mode (Output buffer off) Output mode (Output buffer on)
--Note PM14 PM13 PM12 PM11 PM10
Note To develop a program, these bits must be set to 0. They correspond to PM8 and PM15. While this chip is an input-only device, an emulator has I/O ports.
48
PD75517(A)
(3) Operation of digital I/O ports When an instruction is executed, the operation of the port and pins depends on the I/O mode setting, as listed in Table 4-3. Table 4-3 I/O Port Operations by I/O Instructions
corresponding bit in the mode register is 0 Input mode corresponding bit in the mode register is 1
Input mode
[Output buffer is off] When a 1-bit test instruction, 4-, or 8-bit instruction is executed When a 4-, 8-bit output instruction is executed When a 1-bit output instructionNote is executed Receives data on certain pins.
[Output buffer is on] Receives the contents of the output latch.
Transfers data in the accumulator to the output latch. The contents of the output latch are undefined.
Outputs data in the accumulator to output pins. Changes the output pin state according to the instruction.
Note Instruction such as SET1 PORTn.bit or CLR1 PORTn.bit
49
PD75517(A)
(4) Use of pull-up and pull-down resistors Ports 0 (excluding pin P00/INT4), 1 to 3, 6, and 7 can be provided with pull-up resistors by software. Ports 4, 5, and 12 to 14 can be provided with pull-up resistors by mask options. Port 9 can also be provided with pull-down resistors by mask options. Table 4-4
Port (pin name) Port 0 (P01-P03)Note
Specifying the Use of Pull-Up and Pull-Down Resistors
Specifying the use of pull-up and pull-down resistor The use of pull-up resistors is specified in units of 3 bits by software. The use of pull-up resistors is specified in units of 4 bits by software. Bit in POGA bit 0
Port 1 (P10-P13) Port 2 (P20-P23) Port 3 (P30-P33) Port 6 (P60-P63) Port 7 (P70-P73) Port 4 (P40-P43) Port 5 (P50-P53) Port 12 (P120-P123) Port 13 (P130-P133) Port 14 (P140-P143) Port 9 (P90-P93)
bit 1 bit 2 bit 3 bit 6 bit 7
The use of pull-up resistors is specified in units of bits by mask options.
--
The use of pull-down resistors is specified in units of bits by mask options.
--
Note The P00 pin cannot be provided with a pull-up resistor. Fig. 4-10
Address FDCH
Format of the Register Group A Specifying the Use of Pull-Up Resistors
Symbol POGA Port 0 (P01 - P03) Port 1 (P10 - P13) Port 2 (P20 - P23) Port 3 (P30 - P33) Port 6 (P60 - P63) Port 7 (P70 - P73) Specification contents 0 1 No built-in pull-up resistor provided Built-in pull-up resistor provided
7 PO7
6 PO6
5 --
4 --
3 PO3
2 PO2
1 PO1
0 PO0
50
PD75517(A)
4.2 CLOCK GENERATOR (1) Configuration of the clock generator The clock generator supplies various clock signals to the CPU and peripheral hardware. Fig. 4-11 shows the configuration of the clock generator. Fig. 4-11 Block Diagram of the Clock Generator

* * * * * *
XT1 Subsystem clock generator fXT Clock timer Timer/pulse generator
XT2 X1
Basic interval timer (BT) Timer/event counter Serial interface Clock timer Clock output circuit A/D converter
X2
Main system clock generator
fX 1/2 1/4 1/16
1/8 to 1/4096 Frequency divider
SCC SCC3
Oscillator disable signal
Selector Frequency divider Selector 1/4 CPU clock
SCC0
Internal bus
PCC PCC0
PCC1 4 HALT Note STOP Note PCC2 HALT F/F S
PCC3 R Q
PCC2, PCC3 clear signal
STOP F/F Q S
Wait release signal from BT RESET signal
R
Standby release signal from interrupt control circuit
Note
Instruction execution : Main system clock frequency
Remarks 1. fX
2. fXT : Subsystem clock frequency 3. PCC : Processor clock control register 4. SCC: System clock control register
51
PD75517(A)
(2) Functions of the clock generator The clock generator generates the clock signals listed below, and controls the standby mode and other CPU operation modes. * Main system clock fX * Subsystem clock fXT * CPU clock * Clocks for peripheral hardware The operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The clock generator functions and operates as described below. (a) The generation of a RESET signal selects the lowest-speed modeNote 1 for the main system clock. (PCC = 0, SCC = 0) (b) When the main system clock is selected, the PCC can be set to select one of four CPU clocksNote 2. (c) When the main system clock is selected, the two standby modes, STOP mode and HALT mode, are available. (d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122 s: at 32.768 kHz). In this case, the PCC set value does not affect the CPU clock signal. (e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC. In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock generation cannot be stopped.) (f) Clocks for peripheral hardware are produced by dividing the main system clock signal. Only to the watch timer, the subsystem clock can be directly supplied so that the watch and buzzer output functions can operate continuously even in a standby mode. (g) When the subsystem clock is selected, the watch timer can operate normally, but other hardware cannot be used because they operate with the main system clock. Notes 1. 10.7 s (at 6.0 MHz) or 15.3 s (at 4.19 MHz) 2. 0.67 s, 1.33 s, 2.67 s, 10.7 s (at 6.0 MHz), or 0.95 s, 1.91 s, 3.82 s, 15.3 s (at 4.19 MHz)
52
PD75517(A)
(3) Processor clock control register (PCC) The PCC is a 4-bit register for selecting a CPU clock with the low-order two bits and for selecting a CPU operation mode with the high-order two bits. (See Fig. 4-12.) When bit 3 or bit 2 is set to 1, the standby mode is set. When this is released by the standby release signal, these bits are automatically cleared to return to the normal operation mode. (See Chapter 6 for detailed information.) A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order two bits are set to 0.) Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively. The STOP instruction and HALT instruction can be executed regardless of MBE setting. A CPU clock can be selected only when the main system clock is used for operation. When the subsystem clock is selected for operation, the low-order two bits of the PCC are invalidated, and fXT/4 is automatically set. The STOP instruction can be executed only when the main system clock is used for operation. The generation of a RESET signal clears the PCC to 0. Examples 1. The machine cycle is set to 0.95 s (at 4.19 MHz). SEL MB15 MOV A, #0011B MOV PCC, A 2. The STOP mode is set. (A STOP instruction or HALT instruction must always be followed by an NOP instruction.) STOP NOP
53
PD75517(A)
Fig. 4-12
Address FB3H 3 PCC3 2 1 0 PCC0
Format of the Processor Clock Control Register
Symbol PCC
PCC2 PCC1
CPU clock selection bit Operation with fx = 6.0 MHz SCC = 0 ( ) indicates fX = 6.0 MHz CPU clock frequency 0 0 1 1 0 1 0 1 = fX/64 (93.7 kHz) = fX/16 (375 kHz) = fX/8 (750 kHz) = fX/4 (1.5 MHz) 1 machine cycle 10.7 s s 2.67 s s 1.33 s s 0.67 s s SCC = 1 ( ) indicates f XT = 32.768 kHz CPU clock frequency = fXT/4 (8.192 kHz) Not to be set = fXT/4 (8.192 kHz) 1 machine cycle
s 122 s
s 122 s
Operation with fX = 4.19 MHz SCC = 0 ( ) indicates fX = 4.19 MHz CPU clock frequency 0 0 1 1 0 1 0 1 = fX/64 (65.5 kHz) = fX/16 (262 kHz) = fX/8 (524 kHz) = fX/4 (1.05 MHz) 1 machine cycle 15.3 s s 3.82 s s 1.91 s s 0.95 s s SCC = 1 ( ) indicates f XT = 32.768 kHz CPU clock frequency = fXT/4 (8.192 kHz) Not to be set = fXT/4 (8.192 kHz) 122 s s 1 machine cycle
s 122 s
Remarks 1. 2.
fX : Output frequency from the main system clock oscillator fXT: Output frequency from the subsystem clock oscillator
CPU operation mode control bits 0 0 1 1 0 1 0 1 Normal operation mode HALT mode STOP mode Not to be set
54
PD75517(A)
(4) System clock control register (SCC) The SCC is a 4-bit register for selecting CPU clock with the least significant bit and for controlling the termination of main system clock generation with the most significant bit. (See Fig. 4-13.) SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3 can be manipulated regardless of MBE setting. Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used for operation. The STOP instruction must be used for generation termination when the main system clock is used for operation. The generation of a RESET signal clears the SCC to 0. Fig. 4-13
Address FB7H SCC3 -- -- SCC0
Format of the System Clock Control Register
Symbol SCC
SCC3 SCC0 0 0 1 1 0 1 0 1
CPU clock frequency Main system clock Subsystem clock Not to be set Subsystem clock
Main system clock operation Can oscillate
Oscillation stopped
Cautions 1. A time period of up to 1/fXT is needed to change the system clock. This means that to terminate main system clock generation, SCC.3 must be set when the machine cycles indicated in Table 4-5 or more have elapsed after the clock is switched from the main system clock to the subsystem clock. 2. When the main system clock is used for operation, setting SCC.3 to stop clock generation does not enter the normal STOP mode. 3. When SCC.3 is set to 1, the X1 input pin is connected to VSS (GND electric potential) to prevent leakage in the crystal oscillator. When an external clock is used as the main system clock, never set SCC.3 to 1. 4. When the four bits of PCC are set to 0001B ( = fX/16), do not set SCC.0 to 1. Before switching the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than 0001B is set. When the system operates on the subsystem clock, the PCC bits must also be other than 0001B.
55
PD75517(A)
(5) System clock oscillator The main system clock oscillator operates with a crystal (6.0 MHz standard) or ceramic resonator connected to the X1 and X2 pins. An external clock can also be input. Fig. 4-14 External Circuitry for the Main System Clock Oscillator (b) External clock
(a) Crystal/ceramic oscillation
PD75517(A)
X1 External clock
PD75517(A)
X1
X2 Crystal oscillator or ceramic oscillator
X2
The subsystem clock oscillator operates with a crystal resonator (32.768 kHz standard) connected to the XT1 and XT2 pins. An external clock can also be input. Fig. 4-15 (a) Crystal oscillation External Circuitry for the Subsystem Clock Oscillator (b) External clock
PD75517(A)
XT1 External clock
PD75517(A)
XT1
XT2 32.768 kHz
Open
XT2
A caution on connecting the oscillator is described on the next page.
56
PD75517(A)
Caution When the main system clock or subsystem clock oscillator is used, conform to the following guidelines when wiring at the shaded portions of Fig. 4-14 and 4-15 to eliminate the influence of the wiring capacity. * The wiring must be as short as possible. * Other signal lines must not run in these areas. Any line carrying a high fluctuating current must be kept away as far as possible. * The grounding point of the capacitor of the oscillator must have the same potential as that of VSS. It must not be grounded to ground patterns carrying a large current. * No signal must be taken from the oscillator. When the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator.
57
PD75517(A)
(6) Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the loworder two bits of the PCC. This switching is not performed immediately after the contents of the registers are rewritten, but the system operates with the previous clock for some machine cycles. Accordingly, after this time period, the STOP instruction must be executed or SCC.3 must be set to 1 to terminate main system clock generation. Table 4-5
Setting before switching SCC PCC PCC 0 0 1 0 0
Maximum Time Required to Change the System Clock and CPU Clock
Setting after switching
SCC0 PCC1 PCC0 0 0 0
SCC0 PCC1 PCC0 0 0 1 1 machine cycle
SCC0 PCC1 PCC0 0 1 0 1 machine cycle
SCC0 PCC1 PCC0 0 1 1 1 machine cycle
SCC0 PCC1 PCC0 1 x x fX /64fXT machine cycles (3 machine cycles)
0 0
1
4 machine cycles
4 machine cycles
4 machine cycles
Not to be set
fX/8fXT machine
1
0
8 machine cycles
8 machine cycles
8 machine cycles
cycles (23 machine cycles) fX/4fXT machine
1
1
16 machine cycles 16 machine cycles 16 machine cycles
cycles (46 machine cycles)
1
x
x
1 machine cycle
Not to be set
1 machine cycle
1 machine cycle
Remarks 1. Time enclosed in parentheses is required when fX = 6.0 MHz and fXT = 32.768 kHz. 2. x: Don't care 3. CPU clock is supplied to the CPU. The reciprocal of this frequency is a minimum instruction time (defined as one machine cycle in this manual). Caution When the four bits of PCC are set to 0001B ( = fX/16), do not set SCC.0 to 1. Before switching the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than 0001B is set. When the system operates on the subsystem clock, the PCC bits must also be other than 0001B.
58
PD75517(A)
(7) Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Fig. 4-16. Fig. 4-16 Changing the System Clock and CPU Clock
Commercial power line voltage
ON OFF
VDD pin voltage
RESET signal Wait (31.3 ms) System clock CPU clock fX 15.3 s Internal reset operation fX 0.95 s f XT 122 s fX 0.95 s
fX = 4.19 MHz fXT = 32.768 kHz
1 2 3
The generation of a RESET signal starts CPU operation at the lowest speed of the main system clockNote 1 after a wait timeNote 2 for stable oscillation. The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage on the VDD pin to be high enough for highest-speed operation. The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful), then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to the subsystem clock elapses, SCC.3 is set to terminate main system clock generation.
4
After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at highest speed.
Notes 1. 10.7 s (at 6.0 MHz) or 15.3 s (at 4.19 MHz) 2. 21.8 ms (at 6.0 MHz) or 31.3 ms (at 4.19 MHz)
59
PD75517(A)
4.3 CLOCK OUTPUT CIRCUIT
(1) Configuration of the clock output circuit Fig. 4-17 shows the configuration of the clock output circuit.
(2) Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying clock pulses to a peripheral LSI device. The procedure for outputting a clock pulse signal is as follows:
(a) Select a clock output frequency, and disable clock output. (b) Write a 0 in the P22 output latch. (c) Set the output mode for port 2. (d) Enable clock output.
Fig. 4-17
From the clock generator f X/23 Selector f X/24 f X/2
6
Configuration of the Clock Output Circuit
Output buffer PCL/P22
PORT2.2
CLOM3 0 CLOM1 CLOM0 CLOM
Bit 2 of PMGB
Port 2 input/ output mode specification bit
P22 output latch
4 Internal bus
Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output.
60
PD75517(A)
(3) Clock output mode register (CLOM) The CLOM is a 4-bit register to control clock output. The CLOM is set with a 4-bit memory manipulation instruction. No read operation is allowed on this register. CPU clock is output on the PCL/P22 pin. SEL MB15 ; or CLR1 MBE MOV A, #1000B MOV CLOM, A
Example
The generation of a RESET signal clears the CLOM to 0, disabling clock output.
Fig. 4-18
Address FD0H
Format of the Clock Output Mode Register
Symbol CLOM
3 CLOM3
2 0
1
0
CLOM1 CLOM0
Clock output frequency selection bit (Frequency when fX = 6.0 MHz) 0 0 1 1 0 1 0 1 Output
Note 3
(1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz)
Output fX/2 (750 kHz) Output fX/24 (375 kHz) Output fX/26 (93.7 kHz)
(Frequency when fX = 4.19 MHz) 0 0 1 1 0 1 0 1 Output Note (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz) Output fX/23 (524 kHz) Output fX/24 (262 kHz) Output fX/2 (65.5 kHz)
6
Note is the CPU clock supply selected by PCC. Clock output enable/disable bit 0 1 Output disable Output enable
Caution
Be sure to write a 0 in bit 2 of the CLOM.
61
PD75517(A)
(4) Application to remote control output The clock output function of the PD75517(A) is applicable to remote control output. The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register. Pulse output is enabled or disabled by controlling the clock output enable/disable bit by software. The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output.
Fig. 4-19
CLOM3
Application to Remote Control Output
PCL pin output
62
PD75517(A)
4.4 BASIC INTERVAL TIMER
(1) Configuration of the basic interval timer Fig. 4-20 shows the configuration of the basic interval timer.
(2) Basic interval timer functions The basic interval timer provides the following functions:
(a) Interval timer operation that generates a reference time interrupt (b) Application of watchdog timer for detecting program crashes (c) Selection of a wait time for releasing the standby mode, and counting (d) Reading the count value
Fig. 4-20
From the clock generator fX/25 fX/27 MPX fX/2
9
Configuration of the Basic Interval Timer
Clear signal
Clear signal
Basic interval timer (8-bit frequency divider circuit)
Set signal
BT interrupt request flag
fX/212
BT
IRQBT
Vectored interrupt request signal
3
Wait release signal for standby release BTM0 BTM 8 Internal bus
BTM3 SET1 Note
BTM2
BTM1
4
Note Instruction execution
63
PD75517(A)
(3) Basic interval timer mode register (BTM) BTM is a 4-bit register that controls operation of the basic interval timer. The BTM contents are set by using a 4-bit memory manipulation instruction. Bit 3 can be independently set using a bit manipulation instruction. When bit 3 is set to 1, the contents of the basic interval timer are cleared, and the basic interval timer interrupt request flag (IRQBT) is also cleared (to start the basic interval timer). The generation of a RESET signal clears the contents to 0, and the longest interrupt request signal generation interval time is set.
Examples 1.
Set the interrupt generation interval to 1.95 ms (4.19 MHz). SEL MOV MOV MB15 A, #1111B BTM, A MB15 BTM.3 ; BTM 1111B ; or CLR1 MBE ; Set bit 3 of BTM to 1 ; or CLR1 MBE
2.
Clear BT and IRQBT (application of the watchdog timer) SEL SET1
64
PD75517(A)
Fig. 4-21
Address F85H
Format of the Basic Interval Timer Mode Register
Symbol BTM
3 BTM3
2 BTM2
1 BTM1
0 BTM0
(Frequency when fX = 6.0 MHz) Input clock specification fX/212 (1.46 kHz) fX/29 (11.7 kHz) fX /2 (46.9 kHz) fX/25 (188 kHz) Not to be set
7
Interrupt interval time (wait time for releasing standby) 2 /fX (175 ms) 217/fX (21.8 ms) 215/fX (5.46 ms) 213/fX (1.37 ms) -
20
0
0
0
0
1
1
1
0
1
1
1 Other setting
1
(Frequency when fX = 4.19 MHz) Input clock specification
12
Interrupt interval time (wait time for releasing standby) 2 /fX (250 ms) 217/fX (31.3 ms) 215/fX (7.82 ms) 213/fX (1.95 ms) -
20
0
0
0
fX/2 (1.02 kHz) fX/29 (8.18 kHz) fX /2 (32.768 kHz) fX/2 (131 kHz) Not to be set
5 7
0
1
1
1
0
1
1
1 Other setting
1
Basic interval timer start control bit When "1" is written to this bit, the basic interval timer operation starts (the counter and the interrupt request flag are cleared). When the operation starts, this bit is automatically reset to 0.
65
PD75517(A)
(4) Operation of the basic interval timer The basic interval timer (BT) is always incremented by the clock supplied from the clock generator, and when it overflows, the interrupt request flag (IRQBT) is set. The count operation of BT cannot be stopped. One of four interrupt generation intervals can be selected by setting BTM. (See Fig. 4-21.) The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of BTM to 1 (instruction for starting as an interval timer). The count status can be read by using an 8-bit manipulation instruction. No data can be loaded to the timer. Caution When reading the count value of the basic interval timer, execute a read instruction twice so that unstable data which has been counted will not be read. If the two read values are reasonable, use the second one as the result. If the two read values are far apart, retry from the beginning.
Example
Read the count value of BT. SET1 MBE SEL LOOP: MB15 ; Set the BT address in HL ; First read ; Second read MOV HL, #BT MOV XA, @HL MOV BC, XA MOV XA, @HL SKE BR XA, BC LOOP
To allow the system clock to stabilize after releasing the STOP mode, a wait function is available which stops the operation of the CPU until the basic interval timer overflows. The wait time after generation of a RESET signal is fixed. On the other hand, a wait time can be selected by setting BTM when releasing the STOP mode with an interrupt occurrence. In this case, the wait times are the same as the interval times shown in Fig. 4-21. BTM must be set before the STOP mode is set. (For details, see Chapter 6.)
66
PD75517(A)
4.5 CLOCK TIMER
(1) Clock timer The PD75517(A) contains one channel for a clock timer. Fig. 4-22 shows the configuration of the timer.
(2) Clock timer functions (a) The clock timer sets the test flag (IRQW) every 0.5 seconds. The standby mode can be released with IRQW. (b) Either the main system clock or subsystem clock can produce 0.5-second intervals. (c) The fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program debugging and testing. (d) A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin, so that it can be used for sounding the buzzer and system clock frequency trimming. (e) The frequency divider can be cleared, so the clock can start from zero seconds.
Caution
When the main system clock operates at 6.0 MHz, a time interval of 0.5 s cannot be produced. Before producing this time interval, the main system clock must be changed to the subsystem clock.
Fig. 4-22
Block Diagram of the Clock Timer
fW 2
7
(256 Hz: 3.91 ms)
From the clock generator
fX 128 (32.768 kHz) fXT (32.768 kHz)
fW (32.768 kHz) Selector Frequency divider
fW 2
14
Selector
INTW IRQW set signal
2 Hz 0.5 sec fW (2.048 kHz) 16 Clear signal Output buffer P23/BUZ
WM WM7 0 0 0 0 WM2 WM1 WM0
PORT2.3 P23 output latch
Bit 2 of PMGB
Port 2 input/ output mode
8 Internal bus
Remark The values in parentheses are for fX = 4.194304 MHz and fXT = 32.768 kHz
67
PD75517(A)
(3) Clock mode register The clock mode register (WM) is an 8-bit register that controls the clock timer, and that is set with an 8-bit memory manipulation instruction. Fig. 4-23 shows the format. The generation of a RESET signal clears all bits to 0.
Example
Use the main system clock (4.19 MHz) for setting time, and enable buzzer output. CLR1 MOV MOV MBE XA, #84H WM, XA ; Set WM
Fig. 4-23
Address F98H
Format of the Clock Mode Register
Symbol WM
7 WM7
6 0
5 0
4 0
3 0
2 WM2
1 WM1
0 WM0
Count clock (fW) selection bit 0 WM0 1 Selects subsystem clock: fXT Selects divided system clock output: fX 128
Operation mode selection bit 0 WM1 1 Normal clock mode ( fW 214 : sets IRQW at 0.5 s)
Advanced clock mode (
fW : sets IRQW at 3.91 ms) 27
Clock operation enable/disable bit 0 WM2 1 Enables clock operation Disables clock operation (clears the frequency dividing circuit)
BUZ output enable/disable bit 0 WM7 1 Enables BUZ output Disables BUZ output
68
PD75517(A)
4.6 TIMER/EVENT COUNTER
(1) Configuration of the timer/event counter The PD75517(A) contains one channel of timer/event counter, which is configured as shown in Fig. 4-24.
(2) Functions of the timer/event counter The timer/event counter has the following functions.
(a) Programmable interval timer operation (b) Output of a square wave at a given frequency to the PTO0 pin (c) Event counter operation (d) Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin (e) Supply of serial shift clock signal to a serial interface circuit (f) Function of reading the state of counting
(3) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0) The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter. Fig. 4-25 shows its format. An 8-bit memory manipulation instruction is used to set the timer/event counter mode register. Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to 0 when the timer starts operation.
Examples 1.
The timer is started in the interval timer mode with CP = 4.09 kHz. SEL MOV MOV MB15 XA, #01001100B TM0, XA MB15 TM0.3 ; TM0 4CH ; or CLR1 MBE ; TM0.bit3 1 ; or CLR1 MBE
2.
The timer is restarted according to the setting of the timer/event counter mode register. SEL SET1
The generation of a RESET signal clears all bits to 0. The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT F/F) status to the PTO0 pin. The timer out F/F (TOUT F/F) is inverted by a match signal transmitted from the comparator. The timer out F/F is reset when an instruction sets bit 3 of the timer mode register (TM0). The generation of a RESET signal clears the TOE0 and TOUT F/F to 0.
69
70
8 PORT1.3 Input buffer P13/ TI0 From the clock generator
Fig. 4-24
Block Diagram of the Timer/Event Counter
Internal bus SET1 Note TM0 8 8 TMOD0 Modulo register (8) TOE0
TO enable flag
PORT2.0
P20 output latch signal
Bit 2 of PGMB
TM06 TM05 TM04 TM03 TM02
Port 2 input/ output mode
8
Match
To serial interface TOUT F/F Reset T0 INTT0 Output buffer P20/PTO0
Comparator (8) 8

Count register (8) MPX CP Clear signal
IRQT0 set signal
Timer operation start signal RESET IRQT0 clear signal
(See Fig. 4-11.)
Note Instruction execution
PD75517(A)
PD75517(A)
Fig. 4-25
Address FA0H 7 --
Format of the Timer/Event Counter Mode Register
6 TM06 5 4 3 2 1 -- 0 -- Symbol TM0
TM05 TM04 TM03 TM02
Operation mode Count operation Halts (retains the contents of counting) Count operation
0
1
Timer start specification bit When "1" is written to this bit, the counter and the IRQT0 flag are cleared. Count operation starts if bit 2 has been set to 1.
Count pulse (CP) select bit (Frequency when fX = 6.0 MHz) TM06 TM05 0 0 1 1 1 1 0 0 0 0 1 1 TM04 0 1 0 1 0 1 Count pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (5.86 kHz) fX/28 (23.4 kHz) fX/26 (93.8 kHz) fX/24 (375 kHz) Not to be set
Other setting
(Frequency when fX = 4.19 MHz) TM06 TM05 0 0 1 1 1 1 0 0 0 0 1 1 TM04 0 1 0 1 0 1 Count pulse (CP) TI0 input rising edge TI0 input falling edge fX/210 (4.09 kHz) fX/28 (16.4 kHz) fX/26 (65.5 kHz) fX/24 (262 kHz) Not to be set
Other setting
71
PD75517(A)
Fig. 4-26
Address FA2H
Format of the Timer/Event Counter Output Enable Flag
3 TOE0 Timer/event counter output enable flag (W) 0 1 Disables Enables
(4) Operation mode of the timer/event counter The timer/event counter operates in the count operation disable mode or in the count operation mode, depending on the setting of the mode register. The following operations are possible, regardless of the setting of the mode register:
1 2 3 4 5
P13/TI0 pin signal input and test Output of the timer out F/F status to the PTO0 Setting of the modulo register (TMOD0) Reading from the count register (T0) Setting, clearing, and testing of the interrupt request flag (IRQT0)
(a) Count operation disable mode This mode is set when bit 2 of TM0 is set to 0. In this mode, count operation is not performed because count pulse (CP) supply to the count register is stopped.
72
PD75517(A)
(b) Count operation mode This mode is set when bit 2 of TM0 is set to 1. In this mode, a count pulse signal selected with bits 4 to 6 is supplied to the count register for count operation as shown in Fig. 4-28. Timer operation is usually started in the following steps: 1 2 A count value is set in the modulo register (TMOD0). An operation mode, count clock, and start instruction are set in the mode register (TM0).
An 8-bit data transfer instruction is used to set the modulo register.
Caution A value other than 0 must be set in the modulo register.
Example The value 3FH is set in the modulo register of channel 0. SEL MOV MOV MB15 XA, #3FH TMOD0, XA ; or CLR1 MBE
If the value set in the modulo register matches the contents of the count register, the match signal is generated. Then, the TOUT F/F is inverted, and the counter register is cleared. The interval time of the generation of the match signal is calculated as follows: (Set value of the modulo register + 1) x resolution The resolution is 1/count pulse frequency. Table 4-6 indicates the resolution and maximum set time (when FFH is set in the modulo register), depending on a selected count pulse.
Table 4-6 (When fX = 6.0 MHz)
Mode register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1
Resolution and Maximum Set Time
Timer channel 0 Resolution 171 s 42.7 s 10.7 s 2.67 s Maximum set time 43.7 ms 10.9 ms 2.73 ms 683 s
(When fX = 4.19 MHz)
Mode register TM06 TM05 TM04 1 1 1 1 0 0 1 1 0 1 0 1 Resolution 244 s 61.1 s 15.3 s 3.81 s Timer channel 0 Maximum set time 62.5 ms 15.6 ms 3.91 ms 977 s
73
PD75517(A)
Fig. 4-27 Operation in the Count Operation Mode
INTT0 (IRQT0 set signal)
TI0
Internal clock

MPX
CP
Count register (T0)
Clear signal
Comparator
Match
TOUT F/F
PTO0
Modulo register (TMOD0) To CSI (Only for channel 0)
Fig. 4-28
Timing of Count Operation
Count pulse (CP)
Modulo register
n
Count register
0
1
2
n-1
n
0 Match
1
2
n-1
n
0 Match
1
2
3
4
TOUT F/F
Reset
Timer start specification
74
PD75517(A)
4.7 TIMER/PULSE GENERATOR
(1) Timer/pulse generator functions The PD75517(A) contains one channel for a timer/pulse generator that can be used as a timer or a pulse generator. It has the following functions:
(a) Functions available when the timer/pulse generator is used in the timer mode * 8-bit interval timer operation using one of five clock sources (occurrence of IRQTPG) * Square wave output to the PPO pin
(b) Functions available when the timer/pulse generator is used in the PWM pulse generation mode * PWM pulse output to the PPO pin with an accuracy of 14 bits (applicable for electronic tuning when used as an D/A converter) * Generation of interrupts at regular intervals (215/fX)Note Note 2 15/fX = 5.46 ms (at 6.0 MHz) or 7.81 ms (at 4.19 MHz)
If pulse output is unnecessary, the PPO pin can be used as a 1-bit output port.
Caution
If the timer/pulse generator is operating when the STOP mode is set, it may malfunction. So the timer/pulse generator must be disabled with the mode register in advance.
75
PD75517(A)
(2) Timer/pulse generator mode register (TPGM) The timer/pulse generator mode register (TPGM) is an 8-bit register that controls operation of the timer/ pulse generator. Fig. 4-29 shows the format of the register. TPGM is set with an 8-bit memory manipulation instruction. Bit 3 enables or disables the transfer (reloading) of the timer/pulse generator modulo register (MODH and MODL) contents to the modulo latch. Bit 3 can be manipulated independently of the other bits. By setting TPGM1 to 0, timer/pulse generator operation can be stopped to decrease current consumption. The generation of a RESET signal clears all bits to 0.
Fig. 4-29
Address F90H
Format of Timer/Pulse Generator Mode Register
Symbol TPGM
7 TPGM7
6 --
5
4
3
2 0
1
0
TPGM5 TPGM4 TPGM3
TPGM1 TPGM0
Timer/pulse generator operation mode selection bit TPGM0 0 1 Select PWM pulse generation mode Select timer mode
Timer/pulse generator operation enable/disable bit TPGM1 0 1 Disable timer/pulse generator operation Enable timer/pulse generator operation
Modulo register reload enable/disable bit TPGM3 0 1 Disable reloading of modulo register Enable reloading of modulo register
PPO output latch data TPGM4 0 1 Output 0 to PPO output latch Output 1 to PPO output latch
PPO pin output selection bit static/pulse TPGM5 0 1 Static output on PPO pin Pulse output (square wave/PWM) on PPO pin
PPO pin output enable/disable bit TPGM7 0 1 Disable output on PPO pin (high-impedance) Enable output on PPO pin
76
PD75517(A)
(3) Configuration and operation when the timer/pulse generator is used in the timer mode Fig. 4-30 shows the configuration when the timer/pulse generator is used in the timer mode. The timer mode is selected by setting bit 0 of TPGM to 1. In the timer mode, TPGM3 must be set to 1, allowing a modulo register to be reloaded at any time. In the timer mode, a prescaler is selected with the modulo register L (MODL), and a frequency or interrupt interval value is set in the modulo register H (MODH). The timer starts when the TPGM1 is changed from 0 to 1. Fig. 4-31 shows the operation timing for the MODH setting, and Table 4-7 shows the setting of a frequency or interrupt interval. The output to the PPO pin can be switched between the square wave output and static output. To output a square wave, set TPGM5 and TPGM7 to 1.
Fig. 4-30
Block Diagram of the Timer/Pulse Generator (Timer Mode)
Internal bus
8 MODL Modulo register L (8) TPGM3 (Set to 1)
8 MODH Modulo register H (8)
Modulo latch H (8) 8 Match Comparator (8) Frequency divider fX 1/2 TPGM1 Clear Clear Prescaler select latch (5) T F/F Set Selector
INTTPG IRQTPG set signal Output buffer PPO
CP
8 Count register (8)
TPGM4 TPGM5 TPGM7
77
PD75517(A)
Example Set IRQTPG every 1.95 ms, and set the output high on the PPO pin. CLR1 MOV MOV MOV MOV MOV MOV MBE MODL, XA XA, #0FFH MODH, XA XA, #10011011B TPGM, XA ; Timer start, PPO 1 ; or SEL MB15 XA, #00100000B
Caution
When the timer operating in the timer operation mode is stopped, IRQTPG may be set because T F/F is set. So, the timer must be stopped with an interrupt being disabled, then IRQTPG must be cleared.
Example
DI CLR1 MOV MOV CLR1 EI MBE XA, #0 TPGM, XA IRQTPG
78
PD75517(A)
Fig. 4-31
CP
Timer Mode Operation Timing
MODH Count register T F/F (PPO)
N
0
1
2
N-1
N
0
N
0
N
0
Set TPGM1.
Generate IRQTPG.
Table 4-7 (When fX = 6.0 MHz)
MODL bits 2-6 6 0 0 0 0 1 5 0 0 0 1 0 4 0 0 1 0 0 3 0 1 0 0 0 2 1 0 0 0 0
Modulo Register Settings
Interrupt generation interval (fX = 6.0 MHz) 256 (N+1)/fX = 85.3 s - 10.9 ms 128 (N+1)/fX = 42.7 s - 5.46 ms 64 (N+1)/fX = 21.3 s - 2.73 ms 32 (N+1)/fX = 10.7 s - 1.37 ms 16 (N+1)/fX = 5.33 s - 683 s
Square wave output frequency (fX = 6.0 MHz) fX/256 (N+1) = 91.6 Hz - 11.7 kHz fX/128 (N+1) = 183 Hz - 23.4 kHz fX/64 (N+1) = 366 Hz - 46.9 kHz fX/32 (N+1) = 732 Hz - 93.8 kHz fX/16 (N+1) = 1465 Hz - 188 kHz
(When fX = 4.19 MHz)
MODL bits 2-6 6 0 0 0 0 1 5 0 0 0 1 0 4 0 0 1 0 0 3 0 1 0 0 0 2 1 0 0 0 0 Interrupt generation interval (fX = 4.19 MHz) 256 (N+1)/fX = 122 s - 15.6 ms 128 (N+1)/fX = 61.0 s - 7.81 ms 64 (N+1)/fX = 30.5 s - 3.91 ms 32 (N+1)/fX = 15.3 s - 1.95 ms 16 (N+1)/fX = 7.63 s - 977 s Square wave output frequency (fX = 4.19 MHz) fX/256 (N+1) =64 Hz - 8 kHz fX/128 (N+1) = 128 Hz - 16 kHz fX/64 (N+1) = 256 Hz - 32 kHz fX/32 (N+1) = 512 Hz - 65 kHz fX/16 (N+1) = 1024 Hz - 131 kHz
Cautions 1. A value other than the above cannot be set in MODL. Bits 0, 1, and 7 must be set to 0. 2. N is the set value of MODH. 0 must not be set for N. Be sure to set a value from 1 to 255 for N.
79
PD75517(A)
(4) Configuration and operation when the timer/pulse generator is used in the PWM pulse generation mode Fig. 4-32 shows the configuration when the timer/pulse generator is used in the PWM pulse generation mode. The PWM pulse generation mode is selected by setting TPGM0 to 0. TPGM5 and TPGM7 are set to 1 to enable pulse output. In the PWM mode, the PWM pulse signal can be output on the PPO pin, and IRQTPG can be set at intervals of a fixed time period (215/fX = 5.46 ms: at 6.0 MHz or 215 /fX = 7.81 ms: At 4.19 MHz). PWM pulses output by the PD75517(A) are active-low and have an accuracy of 14 bits. This pulse signal is applicable for electronic tuning and control of a DC motor when it is integrated by an external low-pass filter and is converted to analog voltage. (See Fig. 4-33.) The PWM pulse signal is generated by combining the basic period determined by 210/fX and the secondary period by 215/fX so that the time constant of the external low-pass filter can be decreased. Table 4-8 lists the basic and secondary periods by oscillator frequency.
Table 4-8
Basic and Secondary Periods
fX = 6.0 MHz fX = 4.19 MHz 244 s 7.81 ms
Basic period
(210/fX) (215/fX)
171 s 5.46 ms
Secondary period
The low-level width of a PWM pulse depends on the 14-bit modulo latch value. The upper 8 bits of the modulo latch are transferred from the 8 bits of MODH, and the lower 6 bits of the latch are transferred from the upper 6 bits of MODL. When the PWM pulse signal is converted to analog form, the voltage level of the analog output is obtained as follows:
VAN = Vref x
Value of modulo latch 2 14
Vref: Reference voltage of external switching circuitry
To prevent an incorrect PWM pulse from being output by unstable modulo latch data being rewritten, the
PD75517(A) allows correct data to be written in MODH and MODL beforehand with 8-bit manipulation
instructions, then in the 14-bit data which is to be transferred to the modulo latch at one time. This transfer is referred to as reloading, and it is controlled by TPGM3. If TPGM3 is 0, reloading is disabled, and if it is 1, reloading is enabled. Follow the procedure below to rewrite the modulo latch contents:
(i) (ii) (iii)
Clear TPGM3 to disable reloading. Change the MODH and MODL contents. Set TPGM3 to enable reloading.
Cautions 1. 2. 3.
If the modulo register H (MODH) is set to 0, the PWM pulse generator cannot function normally. So be sure to set MODH to a value from 1 to 255. If the lower 2 bits of the modulo register L (MODL) is read, the read result is unpredictable. If the modulo latch is changed in a shorter period than the PWM pulse basic period 210 /fX (171 s: at 6.0 MHz or 244 s: at 4.19 MHz), PWM pulses do not change.
80
PD75517(A)
Example Decrease analog output voltage to the lowest level, then increase it to the highest level. CLR1 MOV MOV MOV MOV MOV MOV
* * * * * * * * *
MBE XA, #01H MODH, XA XA, #00H MODL, XA XA, #10101010B TPGM, XA ; Enable PWM pulse output ; MODL 00 ; MODH 01
CLR1 MOV MOV MOV MOV SET1
TPGM.3 XA, #0FFH MODH, XA XA, #0FCH MODL, XA TPGM.3
; Disable reloading
; Enable reloading
(5) Static output to the PPO pin When pulse output is unnecessary, the PPO pin can be used as normal static output. In this case, the output data is set in TPGM4 with TPGM5 being set to 0 and TPGM7 to 1.
81
PD75517(A)
Fig. 4-32 Block Diagram of the Timer/Pulse Generator (PWM Pulse Generation Mode)
Internal bus
8 MODH Modulo register H (8)
8 MODL Modulo register L (8)
TPGM3
MODH (8) Modulo latch (14) TPGM1 fX 1/2 Frequency divider
MODL7-2 (6) Output buffer Selector PPO
PWM pulse generator
INTTPG (IRQTPG set signal) (215/fX = 5.46 ms: 6.0 MHz) Note
TPGM5
TPGM7
Note
At 4.19 MHz: 215 /fX = 7.81 ms
Fig. 4-33
Sample Configuration of D/A Conversion Using PD75517(A)
Vref
PD75517 (A)
PPO
PWM signal
Switching circuit
Low-pass filter
VAX (analog voltage)
82
PD75517(A)
4.8 SERIAL INTERFACE (CHANNEL 0)
The PD75517(A) has two channels of serial interface: Channel 0 and channel 1. Table 4-9 lists the differences between channel 0 and channel 1.
Table 4-9
Serial transfer mode, function 3-wire serial I/O Clock selection Transfer method Transfer end flag
Differences between Channel 0 and Channel 1
Channel 0 fX/24 , fX/23, TOUT F/F, external clock Start bit switchable: MSB/LSB Serial transfer end interrupt request flag (IRQCSI0) Available Channel 1 fX/24 , fX/23, external clock Start bit: MSB Serial transfer end flag (EOT)
2-wire serial I/O Serial bus interface (SBI)
Not available
83
PD75517(A)
4.8.1 Serial Interface (Channel 0) Functions The clock synchronous 8-bit serial interface is contained in the PD75517(A) and has four modes. The functions of the four modes are outlined below.
* Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consumption.
* Three-wire serial I/O mode In this mode, 8-bit data is transferred through three lines: Serial clock (SCK0), serial output (SO0), and serial input (SI0). The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher speed. The user can choose 8-bit data transfer starting with the MSB or LSB, so devices starting with either the MSB or LSB can be connected. The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices.
* Two-wire serial I/O mode In this mode, 8-bit data is transferred through two lines: Serial clock (SCK0) and serial data bus (SB0 or SB1). By controlling output levels on the two lines by software, communication with multiple devices is enabled. The output levels of SCK0 and SB0 (or SB1) can be controlled by software, so the user can match an arbitrary transfer format. This means that a line that has been required for handshaking to connect multiple lines can be eliminated for more efficient I/O port utilization.
* Serial bus interface (SBI) mode In this mode, communication with multiple devices can be performed using two lines: Serial clock (SCK0) and serial data bus (SB0 or SB1). This mode conforms to the NEC serial bus format. In this mode, the transmitter can output, on the serial data bus, an address for selecting a device subject to serial communication, commands directed to the remote device, and data. The receiver can identify an address, commands, and data from received data by hardware. This function enables more efficient I/O port utilization as in the case of the two-wire serial I/O mode. In addition, this function can simplify the serial interface control portion of an application program.
4.8.2
Configuration of Serial Interface (Channel 0)
Fig. 4-34 shows the block diagram of the serial interface (channel 0).
84
Fig. 4-34
Block diagram of the Serial Interface (Channel 0)
Internal bus 8/4 CSIM0 Bit test 8 8 8 Slave address register (SVA) (8) Coincidence RELT signal Address comparator P03/SI/SB1 SET CLR SO0 latch Selector Shift register (SIO0) (8) D Q (8) CMDT SBIC Bit manipulation Bit test
ACKE
ACKT
P02/SO/SB0 Selector Bus release/ command/ acknowledge detection circuit P01/SCK0 RELD CMDD ACKD
Busy/ acknowledge output circuit
BSYE
INTCSI0 Serial clock counter INTCSI0 control circuit IRQCSI0 set signal fX/2 4 fX/2 6 fX/2 TOUT F/F (from timer/event counter) External SCK0
3
P01 output latch
Serial clock control circuit
MPX
PD75517(A)
85
PD75517(A)
4.8.3 Register Functions
(1) Serial operation mode register 0 (CSIM0) Fig. 4-35 shows the format of serial operation mode register 0 (CSIM0). CSIM0 is an 8-bit register which specifies a serial interface (channel 0) operation mode, serial clock, wakeup function, and so forth. CSIM0 is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be manipulated bit by bit. Each bit can be manipulated using its name. Each bit may or may not allow read and/or write operation. (See Fig. 4-35.) Bit 6 allows bit test operation only; any data written to this bit is invalid. When the RESET signal is input, this register is set to 00H.
Fig. 4-35
Address 7 FE0H CSIE0 6 COI
Format of Serial Operation Mode Register 0 (CSIM0) (1/3)
Symbol 5 4 3 2 1 0 CSIM0
WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
Serial clock selection bit (W) Serial interface operation mode selection bit (W) Wake-up function specification bit (W) Signal from address comparator (R) Serial interface operation enable/disable specification bit (W)
Remark
(R) : Read only (W) : Write only
86
PD75517(A)
Fig. 4-35 Serial clock selection bit (W)
Serial clock CSIM01 0 0 1 1 CSIM00 3-wire serial I/O mode 0 1 0 1 fX/24 SBI mode 2-wire serial I/O mode Input Output fX/26 (65.5 kHz or 93.8 kHz) Note External clock applied to SCK0 pin Time/event counter output (T0) (262 kHz or 375 kHz)Note SCK0 pin mode
Format of Serial Operation Mode Register 0 (CSIM0) (2/3)
fX/23 (524 kHz or 750 kHz)Note
Note The values in parentheses are for fX = 4.19 MHz or 6.0 MHz. Serial interface operation mode selection bit (W)
Bit sequence of shift register 0 SIO07-0 XA (Transfer starting with MSB) SIO00-7 XA (Transfer starting with LSB) SIO07-0 XA (Transfer starting with MSB)
CSIM04 x
CSIM03 0
CSIM02 0
Operation mode 3-wire serial I/O mode
SO0 pin function SO0/P02 (CMOS output)
SI0 pin function SI0/P03 (Input)
1
0
1
0
SBI mode
SB0/P02 (N-ch open-drain input/output) P02 input
P03 input
1
SB1/P03 (N-ch open-drain input/output) P03 input
0
1
1
2-wire serial I/O mode
SIO07-0 XA (Transfer starting with MSB)
SB0/P02 (N-ch open-drain input/output) P02 input
1
SB1/P03 (N-ch open-drain input/output)
Remark x: Don't care Wake-up function specification bit (W)
WUP 0 1 Sets IRQCSI0 each time serial transfer is completed in each mode. Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state.
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high after releasing BUSY.
87
PD75517(A)
Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (3/3)
Signal from address comparator (R)
COINote Condition for being cleared (COI = 0) When the slave address register (SVA) does not match the data of the shift register Condition for being set (COI = 1) When the slave address register (SVA) matches the data of the shift register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An undefined value may be read during transfer. COI data written by an 8-bit manipulation instruction is ignored.
Serial interface operation enable/disable specification bit (W)
Shift register operation CSIE0 0 1 Shift operation disabled Shift operation enabled Serial clock counter Cleared Count operation IRQCSI0 flag Held Can be set. SO0/SB0, SI0/SB1 pin Used only for port 0 Used in each mode as well as for port 0
Remarks 1. Each mode can be selected by setting CSIE0, CSIM03, and CSIM02.
CSIE0 0 1 1 1 CSIM03 x 0 1 1 CSIM02 x x 0 1 Operation mode Operation halt mode Three-wire serial I/O mode SBI mode Two-wire serial I/O mode
2. The P01/SCK0 pin assumes the following state according to the setting of CSIE0, CSIM01, and CSIM00:
CSIE0 0 1 0 0 0 1 1 1 CSIM01 0 0 1 0 1 1 0 1 CSIM00 0 0 0 1 1 0 1 1 Serial clock output (High level output) Input port High impedance High level output P01/SCK0 pin state
88
PD75517(A)
Remarks 3. When clearing CSIE0 during serial transfer, use the following procedure:
1 2 3
Disable interrupts by clearing the interrupt enable flag. Clear CSIE0. Clear the interrupt request flag.
Examples 1. fX/2 4 is selected as the serial clock, serial interrupt IRQCSI0, is generated each time serial transfer is completed, and serial transfer is performed in the SBI mode with the SB0 pin used as the serial data bus. SEL MB15 ; or CLR1 MBE
MOV XA, #10001010B MOV CSIM0, XA ; CSIM0 10001010B
2.
Serial transfer dependent on the contents of CSIM0 is enabled. SEL MB15 ; or CLR1 MBE
SET1 CSIE0
89
PD75517(A)
(2) Serial bus interface control register (SBIC) Fig. 4-36 shows the format of the serial bus interface control register (SBIC). SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus. SBIC is used mainly in the SBI mode. SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit or 8-bit memory manipulation instruction. Each bit may or may not allow read and/or write operation. (See Fig. 4-36.) When the RESET signal is input, this register is set to 00H.
Caution
Only the following bits can be used in the three-wire and two-wire serial I/O modes:
* Bus release trigger bit (RELT): Sets the SO0 latch. * Command trigger bit (CMDT): Clears the SO0 latch.
Fig. 4-36
Address 7 FE2H BSYE 6
Format of Serial Bus Interface Control Register (SBIC) (1/3)
Symbol 5 ACKE 4 ACKT 3 CMDD 2 RELD 1 CMDT 0 RELT SBIC Bus release trigger bit (W) Command trigger bit (W) Bus release detection flag (R) Command detection flag (R) Acknowledge trigger bit (W) Acknowledge enable bit (R/W) Acknowledge detection flag (R)
ACKD
Busy enable bit (R/W)
Remark
(R) (W)
: Read only : Write only
(R/W) : Read/write
90
PD75517(A)
Fig. 4-36 Bus release trigger bit (W)
RELT Control bit for bus release signal (REL) trigger output. By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.
Format of Serial Bus Interface Control Register (SBIC) (2/3)
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. Command trigger bit (W)
CMDT Control bit for command signal (CMD) trigger output. By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial transfer. Bus release detection flag (R)
RELD 1 2 3 4 Condition for being cleared (RELD = 0) The transfer start instruction is executed. The RESET signal is entered. CSIE0 = 0 (See Fig. 4-35.) SVA does not match SIO0 when an address is received. Condition for being set (RELD = 1) The bus release signal (REL) is detected.
Command detection flag (R)
CMDD 1 2 3 4 Condition for being cleared (CMDD = 0) The transfer start instruction is executed. The bus release signal (REL) is detected. The RESET signal is entered. CSIE0 = 0 (See Fig. 4-35.) Condition for being set (CMDD = 1) The command signal (CMD) is detected.
Acknowledge trigger bit (W)
ACKT When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is automatically cleared to 0.
Cautions 1. 2. 3.
Never set ACKT before or during serial transfer. ACKT cannot be cleared by software. Before setting ACKT, set ACKE = 0.
Acknowledge enable bit (R/W)
ACKE 0 1 Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.) When set before transfer When set after transfer ACK is output in phase with the 9th clock of SCK0. ACK is output in phase with SCK0 immediately following set instruction execution.
91
PD75517(A)
Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (3/3)
Acknowledge detection flag (R)
ACKD 1 2 Condition for being cleared (ACKD = 0) The transfer start instruction is executed. The RESET signal is entered. Condition for being set (ACKD = 1) The acknowledge signal (ACK) is detected (in phase with the rising edge of SCK0).
Busy enable bit (R/W)
1 2 The busy signal is automatically disabled. Busy signal output is stopped in phase with the falling edge of SCK0 immediately after clear instruction execution.
BSYE
0
1
The busy signal is output after the acknowledge signal in phase with the falling edge of SCK0.
Examples 1. A command signal is output. SEL SET1 accordingly. By setting WUP = 1, this interrupt routine is processed only when an address match is found. SEL SKF BR SKT BR CMD : DATA : ADRS : MB15 RELD !ADRS CMDD !DATA
********* ********* *********
MB15 CMDT
; or CLR1 MBE
2. RELD and CMDD are tested to identify the types of received data and the types of processing
; RELD test ; CMDD test ; Command analysis ; Data processing ; Address decode
92
PD75517(A)
(3) Shift register (SIO0) Fig. 4-37 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO0. In transmission, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/SB1). In reception, data is read from the serial input (SI0) or SB0/SB1 into SIO0. Data can be read from or written to SIO0 by using an 8-bit manipulation instruction. When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET signal is entered in the standby mode, the value of SIO0 is preserved. Shift operation is stopped after 8-bit transmission or reception is completed.
Fig. 4-37
Peripheral Hardware of Shift Register 0
Internal bus
Address comparator
RELT CMDT
Shift register (SIO0) SET D CLK CSIM0 Shift clock CLR Q
SO0 latch
BUSY/ACK N-ch open-drain output
The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows: * When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0 is set to 1 after data is written to the shift register 0 is excluded. * When the serial clock is masked after 8-bit serial transfer * SCK0 is high.
93
PD75517(A)
(4) Slave address register (SVA) The slave address register (SVA) has the two functions described below. SVA is manipulated using an 8-bit manipulation instruction. SVA allows only write operation. When the RESET signal is entered, the value of SVA is undefined. However, the value of SVA is preserved when the RESET signal is entered in the standby mode.
* Slave address detection [In the SBI mode] SVA is used when the PD75517(A) is connected as a slave device to the serial bus. SVA is an 8-bit register for a slave to set its slave address (number assigned to it). The master outputs a slave address to the connected slaves to select a particular slave. Two data values (a slave address output from the master and the value of SVA) are compared with each other by the address comparator. If a match is found, the slave is selected. At this time, bit 6 (COI) of serial operation mode register 0 (CSIM0) is set to 1.
Cautions 1. Slave selection or nonselection state is detected by detecting a match for a slave address received after bus release (in the state of RELD = 1). For this match detection, an address match interrupt (IRQCSI0) generated when WUP is set to 1 is usually used. So detect selection/nonselection state by slave address when WUP is set to 1. 2. When detecting selection/nonselection state without using an interrupt when WUP is 0, do not use the address match detection method. Instead, use transfer of commands set in advance in a program.
* Error detection [In the two-wire serial I/O mode or SBI mode] SVA detects an error in either of the following cases: * When addresses, commands, or data is transferred with the PD75517(A) operating as the master * When data is transferred with the PD75517(A) operating as a slave
4.8.4 Signals Table 4-10 lists signals. Fig. 4-38 to 4-43 show operations of signals and flags.
94
Table 4-10
Various Signals (1/2)
Signal name
Output device Master
Definition
Timing chart
Condition for output * RELT is set.
Flag operation * RELD is set. * CMDD is cleared.
Meaning of signal Indicates that CMD signal follows and data transmitted is address data.
Bus release signal (REL)
Rising edge of SB0 (SB1) when SCK0 = 1
SCK0 SB0 (SB1)
"H"
Command signal (CMD)
Master
Falling edge of SB0 (SB1) when SCK0 = 1
* CMDT is set. SCK0 SB0 (SB1) "H"
* CMDD is set.
(1) Data transmitted after REL signal output is address. (2) (Data transmitted, with REL signal not being output, is command. Indicates completion of reception.
Acknowledge signal (ACK)
Master/ slave
Low level signal output on SB0 (SB1) during one SCK0 clock cycle after serial reception is completed SCK0
1 # ACKE = 1 2 ACKT is set. $
* ACKD is set.
9 BUSY READY BUSY ACK READY * BSYE = 1
Busy signal (BUSY)
Slave
Low level signal output on SB0 (SB1) after acknowledge signal High level signal output on SB0 (SB1) before serial transfer is started or after serial transfer is completed
SB0 (SB1) D0 ACK SB0 (SB1) D0
-
Indicates that serial transfer is disabled because processing is in progress.
PD75517(A)
Ready signal (READY)
Slave
1 BSYE = 0 # 2 Execution of $ instruction to write data to SIO0 (Transfer start request)
Indicates that serial transfar is enabled.
-
95
96
Signal name Output device Master Definition Serial clock (SCK0) Synchronous clock for outputting address/ command/data, ACK signal, synchronous BUSY signal, and so on. Address/command/data is output during first 8 clock cycles. Address (A7 - A0) Master 8-bit data transferred in phase with SCK0 after REL signal and CMD signal output Command (C7 - C0) Master 8-bit data transferred in phase with SCK0 after only CMD signal is output, with REL signal not being output Data (D7 - D0) Master/ slave 8-bit data transferred in phase with SCK0, with neither REL signal nor CMD signal being output SCK0 SB0 (SB1) SCK0 SB0 (SB1) SCK0 SB0 (SB1) SCK0 SB0 (SB1)
Table 4-10
Various Signals (2/2)
Timing chart
Condition for output Execution of instruction to write data to SIO0 when CSIE0 = 1 (serial transfer start request) Note 2
Flag operation IRQCSI0 is set (on rising edge of 9th clock) Note 1
Meaning of signal Timing of signal output on serial data bus
1
2
7
8
9
10
1
2
7
8
Address of slave device on serial bus
REL
CMD Directions and messages to slave device
1
2
7
8
CMD Data processed by slave or master
1
2
7
8
Notes 1. When WUP = 0, IRQCSI0 is always set on the 9th rising edge of SCK0. When WUP = 1, IRQCSI0 is set on the 9th rising edge of SCK0 only if a received address matches the value of the slave address register (SVA). 2. If the BUSY state is present, data transfer is started after the READY state is set.
PD75517(A)
PD75517(A)
Fig. 4-38 Operations of RELT, CMDT, RELD, and CMDD (Master)
Transfer start request SIO0
SCK0
SB0 (SB1)
RELT
CMDT
RELD
CMDD
Fig. 4-39
Operations of RELT, CMDT, RELD, and CMDD (Slave)
Write to SIO0.
Transfer start request SIO0
SCK0
1
2
7
8
SO0 latch
D7
D6
D1
D0
RELT (Master) CMDT (Master) When address match is found RELD When address mismatch is found CMDD
Fig. 4-40
SCK0 6 7 8 9
Operation of ACKT
SB0 (SB1)
D2
D1
D0
ACK
ACK signal is output during first clock cycle immediately after ACKT is set.
ACKT
When set during this period
Caution Do not set the ACKT until the transfer is completed.
97
PD75517(A)
Fig. 4-41 Operation of ACKE
(a) When ACKE = 1 at time of transfer completion
SCK0
1
2
7
8
9 The ACK signal is output during the ninth clock cycle
SB0/SB1
D7
D6
D2
D1
D0
ACK
ACKE When ACKE = 1 at this point
(b) When ACKE is set after transfer completion
SCK0
6
7
8
9 The ACK signal is output during the first clock cycle immediately after ACKT is set.
SB0/SB1
D2
D1
D0
ACK
ACKE
When ACKE is set during this period and ACKE = 1 at the falling edge of the next SCK0
(c) When ACKE = 0 at time of transfer completion
SCK0
1
2
7
8
9 The ACK signal is not output
SB0/SB1
D7
D6
D2
D1
D0
ACKE
When ACKE = 0 at this point
(d) When ACKE = 1 period is too short
SCK0 The ACK signal is not output
SB0/SB1
D2
D1
D0
ACKE
When ACKE is set or cleared during this period, and ACKE = 0 at the falling edge of SCK0
98
PD75517(A)
Fig. 4-42 Operation of ACKD
(a) When ACK signal is output during ninth SCK0 clock
Transfer start request SIO0 Transfer start SCK0 6 7 8 9
SB0/SB1
D2
D1
D0
ACK
ACKD
(b) When ACK signal is output after ninth SCK0 clock
Transfer start request SIO0 Transfer start SCK0 6 7 8 9
SB0/SB1
D2
D1
D0
ACK
ACKD
(c) Clear timing for case where start of transfer is requested during BUSY
Transfer start request SIO0
SCK0
6
7
8
9
SB0/SB1
D2
D1
D0
ACK
BUSY
D7
D6
ACKD
Fig. 4-43
SCK0
Operation of BSYE
6
7
8
9
SB0/SB1
ACK
BUSY
BSYE
When BSYE = 1 at this point
When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK0.
99
PD75517(A)
4.8.5 Serial Interface (Channel 0) Operation
(1) Operation halt mode The operation halt mode is used when serial transfer is not performed. This mode reduces power consumption. The shift register 0 does not perform shift operation in this mode, so the shift register can be used as a normal 8-bit register. When the RESET signal is entered, the operation halt mode is set. The P02/SO0/SB0 pin and P03/SI0/SBI pin function as input-only port pins. The P01/SCK0 pin can be used as an input port pin by setting the serial operation mode register 0.
(2) Three-wire serial I/O mode operations The three-wire serial I/O mode is compatible with other modes used in the 75X series, PD7500 series, and 78K series. Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial input (SI0).
(a) Communication operation The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. The shift register performs shift operation on the falling edge of the serial clock (SCK0). Transmit data is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0 pin is latched in the shift register 0 on the rising edge of SCK0. When eight bits have been transferred, shift register 0 operation automatically terminates setting the interrupt request flag (IRQCSI0).
Fig. 4-44
Timing of Three-Wire Serial I/O Mode
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQCSI0 Completion of transfer Transfer is started in phase with falling edge of SCK0. Execution of instruction that writes data to SIO0 (Transfer start request)
100
PD75517(A)
The SO0 pin becomes a CMOS output and outputs the state of the SO0 latch. So the output state of the SO0 pin can be manipulated by setting the RELT bit and CMDT bit. However, this manipulation must not be performed during serial transfer.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output mode (internal system clock mode). (See Section 4.8.7.)
(b) Switching between MSB and LSB as the first transfer bit The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first bit of transfer. Fig. 4-45 shows the configuration of shift register 0 (SIO0) and internal bus. As shown in Fig. 4-45, read or write operation can be performed by switching between the MSB and LSB. This switching can be specified using bit 2 of serial operation mode register 0 (CSIM0).
Fig. 4-45
7 6 Internal bus 1 0 LSB first MSB first
Transfer Bit Switching Circuit
Read/write gate
Read/write gate
SO0 latch SI0 Shift resister0 (SIO0) D Q
SO0 SCK0
The first bit is switched by changing the order of data bits written to shift register 0 (SIO0). The shift operation order of SIO0 is always the same. Accordingly, the first bit must be switched between the MSB and LSB before writing data to the shift register 0.
101
PD75517(A)
(3) Two-wire serial I/O mode The two-wire serial I/O mode can be made compatible with any communication format by programming. In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial data input/output (SB0 or SB1).
(a) Communication operation The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Transmit data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with the MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register on the rising edge of SCK0. When eight bits have been transferred, shift register 0 operation automatically terminates setting the interrupt request flag (IRQCSI0).
Fig. 4-46
Timing of Two-Wire Serial I/O Mode
SCK0
1
2
3
4
5
6
7
8
SB0/SB1
D7
D6
D5
D4
D3
D2
D1
D0
IRQCSI0 Completion of transfer Transfer is started in phase with falling edge of SCK0. Execution of instruction that writes date to SIO0 (Transfer start request)
The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so the voltage level on that pin must be pulled up externally. The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states can be controlled by setting the RELT or CMDT bit. However, this operation must not be performed during serial transfer.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output mode (internal system clock mode). (See Section 4.8.7.)
102
PD75517(A)
(4) SBI mode operation The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format. To allow communication with multiple devices on a single-master and high-speed serial bus using two signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method. So the SBI can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are used to configure a serial bus. Fig. 4-47 is an example of the SBI system configuration.
Fig. 4-47
Example of SBI System Configuration
+VDD
SB0 (SB1) Master CPU SCK0
Serial data bus Serial clock
SB0 (SB1) SCK0
Slave CPU Address 1
SB0 (SB1) SCK0
Slave CPU Address 2
SB0 (SB1) SCK0
Slave IC Address N
Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data bus line. 2. To switch between the master and slave, a pull-up resistor is required also for the serial clock line (SCK0), because SCK0 input/output switching is performed between the master and slave asynchronously.
103
PD75517(A)
(a) SBI functions * Address/command/data identification function Serial data is classified into three types: Address, command, and data. * Address-based chip select function The master selects a chip by address transfer. * Wake-up function A slave can easily check address reception (for chip select identification) with the wake-up function. This function can be set or released by software. When the wake-up function is set, an interrupt (IRQCSI0) is generated when a match address is received. For this reason, in communication with multiple devices, a CPU other than a selected slave can operate independently of serial communication. * Acknowledge signal (ACK) control function The acknowledge signal, which is used to confirm the reception of serial data, can be controlled. * Busy signal (BUSY) control function The busy signal, which is used to post the busy state of a slave, can be controlled.
104
PD75517(A)
Fig. 4-48 Address transfer
SCK0 8 9
Timing of SBI Transfer
SB0/SB1 Bus release signal
A7
A0
ACK
BUSY
Command transfer
SCK0
Command signal 9
SB0/SB1
C7
C0 ACK
BUSY
READY
Data transfer
SCK0
8
9
SB0/SB1
D7
D0 ACK
BUSY
READY
(b) Communication operation In the SBI mode, the master usually selects a slave device to communicate with from multiple devices by outputting the address of the slave in the serial bus. After selecting a device to communicate with, the master exchanges commands and data with the slave device, thus establishing serial communication. Fig. 4-49 to 4-52 show the timing charts of data communication operations. In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Transmit data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on the rising edge of SCK0.
105
106
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 pin SB0 pin Slave device processing (receiver) Program processing Hardware operation
Fig. 4-49
Address Transmission from Master Device to Slave Device (WUP = 1)
Set CMDT
Set Set RELT CMDT
Write to SIO0
Interrupt handling (preparation for next serial transfer)
Serial transmission
Generate IRQCSI0
Set ACKD
Stop SCK0
1
2
3
4
5
6
7
8
9
A7
A6
A5
A4
A3
A2
A1
A0
ACK
BUSY
READY
Address
WUP0
Set ACKT
Clear BUSY
Set Clear Set CMDD CMDD CMDD Set RELD
Serial reception
Generate IRQCSI0
Output Output ACK BUSY
Clear BUSY
(When SVA = SIO0)
PD75517(A)
Fig. 4-50
Command Transmission from Master Device to Slave Device
Master device processing (transmitter)
Set CMDT
Program processing
Write to SIO0
Interrupt handling (preparation for next serial transfer)
Hardware operation
Serial transmission
Generate IRQCSI0
Set ACKD
Stop SCK0
Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9
SB0 pin
C7
C6
C5
C4
C3
C2
C1
C0
ACK
BUSY
READY
Command Slave device processing (receiver) Read SIO0
Analyze command
Program processing
Set ACKT
Clear BUSY
Hardware operation
Set CMDD
Serial reception
Generate IRQCSI0
Output Output BUSY ACK
Clear BUSY
PD75517(A)
107
108
Master device processing (transmitter) Program processing Hardware operation Transfer line SCK0 pin SB0 pin Slave device processing (receiver) Program processing Hardware operation
Fig. 4-51
Data Transmission from Master Device to Slave Device
Write to SIO0
Interrupt handling (preparation for next serial transfer)
Serial transmission
Generate IRQCSI0
Set ACKD
Stop SCK0
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY
READY
Read SIO0
Set ACKT
Clear BUSY
Serial reception
Generate IRQCSI0
Output Output BUSY ACK
Clear BUSY
PD75517(A)
Fig. 4-52
Data Transmission from Master Device to Slave Device
Master device processing (receiver)
Write FFH to SIO0 Read Write Set FFH to SIO0 SIO0 ACKT
Program processing
Receive data processing
Hardware operation
Stop SCK0
Serial reception
Generate IRQCSI0
Output ACK
Serial reception
Transfer line SCK0 pin 1 2 3 4 5 6 7 8 9 1 2
SB0 pin
BUSY
READY
D7
D6
D5
D4 Data
D3
D2
D1
D0
ACK
BUSY READY
D7
D6
Slave device processing (transmitter) Write to SIO0 Write to SIO0
Program processing
Hardware operation
Clear BUSY
Serial transmission
Generate IRQCSI0
Set ACKD
Output BUSY
Clear BUSY
PD75517(A)
109
PD75517(A)
4.8.6 Transfer Start in Each Mode In each of the three-wire serial I/O, two-wire serial I/O, and SBI modes, serial transfer is started by writing transfer data in shift register 0 (SIO0). However, the following two conditions must be satisfied:
* The serial interface operation enable/disable bit (CSIE0) is set to 1. * The internal serial clock is not operating after 8-bit serial transfer, or SCK0 is high.
Caution Transfer cannot be started by setting CSIE0 to 1 after writing data to the shift register 0.
When eight bits have been transferred, serial transfer automatically terminates setting the interrupt request flag (IRQCSI0).
[In the two-wire serial I/O mode] Caution The N-ch transistor needs to be turned off when data is received. So FFH must be written to SIO0 beforehand.
[In the SBI mode] Cautions 1. The N-ch transistor needs to be turned off when data is received. So FFH must be written to SIO0 beforehand. However, when the wake-up function specification bit (WUP) is set to 1, the N-ch transistor is always off. So FFH need not be written to SIO0 beforehand for reception. 2. If data is written to SIO0 when the slave is busy, the data is not lost. Transfer is started when the busy state is released and input to SB0 (or SB1) goes high.
Example When RAM data specified by the HL register is transferred to SIO0, SIO0 data is loaded into the accumulator at the same time, and serial transfer is started.
MOV SEL XCH
XA, @HL MB15 XA, SIO0
; Extracts transmit data from RAM ; or CLR1 MBE ; Exchanges transmit data with receive data and starts transfer
110
PD75517(A)
4.8.7 Manipulation of SCK0 Pin Output The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation in addition to normal serial clock output. The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/SB0/ SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.) The procedure for manipulating SCK0/P01 pin output is explained below.
1
Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode). When serial transfer is halted, SCK0 from the serial clock control circuit is set to 1.
2
Manipulate the P01 output latch by using a bit manipulation instruction.
Example To output one clock cycle on the SCK0/P01 pin by software SEL MOV MOV CLR1 SET1 MB15 ; or CLR1 MBE XA, #10000011B ; SCK0 (fX/23), output mode CSIM0, XA 0FF0H.1 0FF0H.1 ; SCK0/P01 0 ; SCK0/P01 1
Fig. 4-53
SCK0/P01 Pin Circuit Configuration
Address FF0H.1 P01 output latch From the serial clock control circuit
P01/SCK0
To internal circuit
SCK0 When CSIE0=1 and CSIM01 and CSIM00 are not 00
The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.
Cautions 1. 2.
During normal serial transfer, the P01 output latch must be set to 1. The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The address of the latch (0FF0H.1) must be coded in the operand of an instruction directly. However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is executed. CLR1 PORT0.1 SET1 PORT0.1 CLR1 0FF0H.1 SET1 0FF0H.1 Allowed Not allowed
111
PD75517(A)
4.9 4.9.1 SERIAL INTERFACE (CHANNEL 1) Serial Interface (Channel 1) Functions
The PD75517(A) has two modes. The functions of the two modes are outlined below. * Operation halt mode This mode is used when serial transfer is not performed. This mode reduces power consumption. * Three-wire serial I/O mode 8-bit data transfer is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input (SI1). The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher speed. Eight-bit data transfer always starts the MSB. The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many other types of peripheral I/O devices. 4.9.2 Serial Interface (Channel 1) Configuration Fig. 4-54 shows the block diagram of the serial interface (channel 1).
112
Fig. 4-54
Block Diagram of the Serial Interface (Channel 1)
Internal bus Bit manipulation 8 bit 0 P83/SI1 Shift register 1 (8) SIO1 write signal (serial start signal) 7 SIO1 bit 7 Serial operation mode register 1 (8) 8 0 CSIM1 Bit manipulation
P82/SO1
Clear Serial clock counter (3) Overflow Set Serial transfer end flag (EOT)
Clear P81/SCK1 R Q S fX/23 MPX fX/24
PD75517(A)
113
PD75517(A)
4.9.3 Register Functions
(1) Serial operation mode register 1 (CSIM1) Fig. 4-55 shows the format of serial operation mode register 1 (CSIM1). CSIM1 is an 8-bit register which specifies a serial interface (channel 1) operation mode and serial clock. CSIM1 is manipulated using an 8-bit memory manipulation instruction. Only the high-order one bit can be manipulated independently. Each bit can be manipulated using its name. When the RESET signal is input, this register is set to 00H. Fig. 4-55
Address 7 FC8H CSIE1 6 0 5 0 4 0 3 0 2 0 1 0 CSIM1 CSIM11 CSIM10
Format of Serial Operation Mode Register 1 (CSIM1)
Symbol
Serial clock selection bit (W) Serial interface operation enable/disable specification bit (W)
Remark
(W): Write only
Serial clock selection bit (W)
CSIM11 0 0 1 1 CSIM10 0 1 0 1 Serial clock (3-wire serial I/O mode) External clock applied to SCK1 pin Not to be set fX/24 (262 kHz or 375 kHz)Note fX/23 (524 kHz or 750 kHz)Note Output SCK1 pin mode Input
Note
The values at 4.19 MHz and 6.0 MHz are indicated in parentheses.
Serial interface operation enable/disable specification bit (W)
Shift register operation CSIE1 0 1 Shift operation disabled Shift operation enabled
Serial clock counter Cleared Count operation Held
EOT flag
SO1, SI1 pin Used only for port 8 Used in serial interface as well as for port 8
Can be set.
Caution
Be sure to write 0 in bits 2 to 6 of the serial operation mode register 1 (CSIM1).
114
PD75517(A)
Example To select fX/24 as the serial clock, and set the serial transfer end flag EOT to 1 each time serial transfer terminates SEL MB15 ; Or CLR1 MBE ; CSIM1 10000010B MOV XA, #10000010B MOV CSIM1, XA (2) Shift register 1 (SIO1) SIO1 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock. Serial transfer is started by writing data to SIO1. The MSB is used as the first bit of transfer. In transmission, data written to SIO1 is output on the serial output (SO1). In reception, data is read from the serial input (SI1) into SIO1. Data can be read from or written to SIO1 using an 8-bit manipulation instruction. When the RESET signal is entered during operation, the value of SIO1 is undefined. When the RESET signal is entered in the standby mode, the value of SIO1 is preserved. Shift operation is stopped after 8-bit transmission or reception is completed. The timing for reading SIO1 and start of serial transfer (writing to SIO1) is as follows: * When the serial interface operation enable/disable bit (CSIE1) is set to 1. However, the case where CSIE1 is set to 1 after data is written to the shift register 1 is excluded. * When the serial clock is masked after 8-bit serial transfer * When SCK1 is high 4.9.4 Serial Interface (Channel 1) Operation
(1) Operation halt mode The operation halt mode is used when serial transfer is not performed, which is set by setting 0 in CSIE1. This mode reduces power consumption. Shift register 1 does not perform shift operation in this mode, so the shift register can be used as a normal 8-bit register. When the RESET signal is entered, the operation halt mode is set. The P82/SO1 pin and P83/SI1 pin function as input-only port pins. The P81/SCK1 pin can be used as an input port pin by setting serial operation mode register 1.
115
PD75517(A)
(2) Three-wire serial I/O mode operations The three-wire serial I/O mode is compatible with other modes used in the 75X series, PD7500 series, and 78K series. This mode is set by setting CSIE1 to 1. Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input (SI1). The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit by bit in phase with the serial clock. Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Transmit data is latched on the SO1 latch, and is output on the SO1 pin. Receive data applied to the SI1 pin is latched in the shift register 1 on the rising edge of SCK1. When eight bits have been transferred, operation of shift register 1 automatically terminates setting the serial transfer end flag (EOT). Setting the serial transfer and flag (EOT) cannot release the standby function. Fig. 4-56 Timing of the Three-Wire Serial I/O Mode
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
EOT Completion of transfer Transfer is started in phase with falling edge of SCK1. Execution of instruction that writes data to SIO1 (Transfer start request)
Example
To transfer the RAM data specified by the HL register pair to SIO1, load the SIO1 data to the accumulator, and start serial transfer: MOV XA, @HL SEL XCH MB15 XA, SIO1 ; Fetch transmit data from RAM ; Or CLR1 MBE ; Exchange transmit data and receive data, and start transfer
116
PD75517(A)
4.10 A/D CONVERTER
The PD75517(A) contains an 8-bit analog/digital (A/D) converter that has eight analog input channels (AN0 to AN7). The A/D converter employs the successive-approximation method. (1) Configuration of the A/D converter Fig. 4-57 shows the configuration of the A/D converter. Fig. 4-57 Block Diagram of the A/D Converter
Internal bus
8
0
ADM6 ADM5 ADM4
SOC
EOC
ADM1
0
ADM
8
AN0 AN1 AN2
Control circuit Sample and hold circuit
+ AN3 AN4 AN5 AN6 Multiplexer - Comparator
SA register (8)
8 AN7
Tap decoder
AVREF R/2 R R R R/2
AVSS
117
PD75517(A)
(2) Pins of the A/D converter (a) AN0 to AN7 AN0 to AN7 are the input pins for eight analog signal channels. Analog signals subject to A/D conversion are applied to these pins. The A/D converter contains a sample-and-hold circuit, and analog input voltages are internally maintained during A/D conversion. (b) AVREF, AVSS A reference voltage for the A/D converter is applied to these pins. By using an applied voltage across AVREF and AVSS, signals applied to AN0 to AN7 are converted to digital signals. AVSS must be always VSS. (3) A/D conversion mode register The A/D conversion mode register (ADM) is an 8-bit register which operates as follows: * Selects analog input channels. * Selects comparator bias voltage. Note * Directs the start of conversion and detects the completion of conversion. ADM is set with an 8-bit manipulation instruction. Bit 2 (EOC) and bit 3 (SOC) can be manipulated on a bit-by-bit basis. The generation of a RESET signal initializes ADM to 04H. That is, only EOC is set to 1, with all bits cleared to 0. Note If the reference voltage (AVREF) of the A/D converter does not exceed 0.65VDD, the accuracy of conversion may be lowered. To correct such lowered accuracy, selecting comparator bias voltage is provided.
118
PD75517(A)
Fig. 4-58
Address 7 FD8H 0 6 ADM6 5 ADM5 4 ADM4 3 SOC 2 EOC 1 ADM1 0 0 ADM
Format of the A/D Conversion Mode Register
Symbol
Comparator bias voltage selection 0 ADM1 1 AVREF 0.6VDD AVREF 0.65VDD
Reamark This bit may be set to either 0 or 1 for 0.6VDD AVREF 0.65VDD. End of conversion flag (R) 0 EOC 1 Conversion completed Conversion under way
Start of conversion bit (W) Setting this bit starts conversion. After conversion is started, the bit is reset automatically.
SOC
Analog channel selection bit (W) ADM6 0 0 0 0 1 1 1 1 ADM5 0 0 1 1 0 0 1 1 ADM4 0 1 0 1 0 1 0 1 Analog channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Caution A/D conversion is started a maximum of 24/fX seconds (2.67 s at fX = 6.0 MHz)Note after SOC is set. (For details, see item (5).) Note 2 4/fX seconds = 3.81 s for fX = 4.19 MHz
119
PD75517(A)
(4) SA register (successive approximation register) The SA register is an 8-bit register to hold the result of A/D conversion in successive approximation. SA is read with an 8-bit manipulation instruction. No data can be written to SA by software. The generation of a RESET signal makes SA undefined. SA is mapped to address FDAH. (5) A/D converter operation Analog input signals subject to A/D conversion are specified by setting bits 6, 5, and 4 in the A/D conversion mode register (ADM6, ADM5, and ADM4). Comparator bias voltage selection is specified by setting bit 1 in the A/D conversion mode register (ADM1). A/D conversion is started by setting bit 3 (SOC) of ADM to 1. After that, SOC is automatically cleared to 0. A/D conversion is performed by hardware using the successive-approximation method. The resultant 8-bit data is loaded into the SA register. Upon completion of A/D conversion, ADM bit 2 (EOC) is set to 1. Fig. 4-59 shows the timing chart of A/D conversion. The A/D converter is used as follows: 1 2 3 4 Select analog input channels and comparator bias voltage (by setting ADM6, ADM5, ADM4, and ADM1). Direct the start of A/D conversion (by setting SOC). Wait for the completion of A/D conversion (wait for EOC to be set or wait using a software timer). Read the result of A/D conversion (read the SA register).
Cautions 1. 1 and 2 above can be performed at the same time. 2. There is a delay of up to 24/fX seconds (fX = 6.0 MHz: 2.67 s, or fX = 4.19 MHz: 3.81 s) from the setting of SOC to the clearing of EOC after A/D conversion is started. EOC must be tested when a time indicated in Table 4-11 has elapsed after the setting of SOC. Table 4-11 also indicates A/D conversion times. Table 4-11
Setting values of SCC, PCC A/D conversion time SCC1 SCC0 PCC1 PCC0 0 0 0 0 1 1 0 1 1 x x x 0 1 x x Conversion stopped 2 machine cycles 4 machine cycles Waiting not required -- 21 machine cycles 42 machine cycles Waiting not required -- 0 1 168/fX sNote (28.0 s/fX = 6.0 MHz)
Setting of SCC and PCC
Wait time from SOC setting Wait time from SOC setting to A/D conversion completo EOC test tion Waiting not required 1 machine cycle 3 machine cycles 11 machine cycles
Note
40.1 s for fX = 4.19 MHz x: Don't care
Remark
120
PD75517(A)
Fig. 4-59
SOC EOC SA register Previous data Undefined Result of conversion
Timing Chart of A/D Conversion
Time elapsed before A /D conversion starts (Maximum of 24/fX s)
Sampling time A /D conversion 168/fX s Note
Note
28 s (for fX = 6.0 MHz) or 40.1 s (for fX = 4.19 MHz)
Fig. 4-60 shows the relationship between analog input voltages and 8-bit digital data obtained by A/D conversion. Fig. 4-60 Relationship (Ideal) between Analog Input Voltages and Results of A/D Conversion
FFH
FEH
Digital conversion result
FDH
03H
02H
01H
00H 0 1 ---- 256 2 ---- 256 3 ---- 256 253 ---- 256 254 ---- 256 255 ---- 256 1 (x AVREF)
Analog input voltage (V)
121
PD75517(A)
(6) Notes on the standby mode The A/D converter operates with the main system clock. So its operation stops in the STOP mode, or when the subsystem clock is used, in the HALT mode. A current flows through the AVREF pin even when the A/D converter is stopped, so that the current must be stopped to reduce overall system power consumption. Since the P113 pin has a higher drive capability than the other ports, it can supply voltage to the AVREF pin directly. In this case, however, the actual AVREF voltage does not provide precision. This means that the value resulting from conversion does not provide precision and can be used only for relative comparison. In the standby mode, outputting a low on the P113 can reduce power consumption. Fig. 4-61 Reducing Power Consumption in the Standby Mode
VDD
P-ch Note P113
AVREF .. AVREF = VDD
PD75517(A)
AVSS
Note
The drive capability of P-ch is higher than that of other ports.
122
PD75517(A)
(7) Other notes on use (a) AN0 to AN7 input range Specified voltages must be applied to AN0 to AN7 inputs. If a voltage higher than VDD or lower than VSS is applied even when the maximum absolute rating is not exceeded, the conversion result for an associated channel becomes unpredictable. In addition, the conversion results for other channels may be affected. (b) Noise protection To maintain 8-bit resolution, the user should pay attention to noise that may be applied to the AVREF, and AN0 to AN7 pins. Noise adversely affects operation to a greater extent when the analog input source has a higher output impedance. As shown in Fig. 4-62, a capacitor should be externally connected. Fig. 4-62 Analog Input Pin Connection
VDD
If it is anticipated that noise voltages do not fall in the range of VSS to VDD, clamp this point using a diode with a low Vf (not higher than 0.3 V).
AVREF, AN0 to AN7 C = 100 - 1000 pF C
PD75517(A)
AVSS
VSS
AN4/P150 to AN7/P153 pins The analog input pins (AN4 to AN7) are also used for an input port (PORT15). When any of AN4 to AN7 is selected for A/D conversion, no input instruction must be executed for PORT15 during A/D conversion. Otherwise, the accuracy of conversion may deteriorate. If a digital pulse signal is applied to a pin adjacent to a pin being used for A/D conversion, an expected A/D conversion value may not be obtained because of coupling noise. So no digital pulse signal should be applied to the adjacent pin being used for A/D conversion.
123
PD75517(A)
4.11 BIT SEQUENTIAL BUFFER: 16 BITS
The bit sequential buffer is special data memory for bit manipulations. In particular, the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications. So the buffer is useful in processing long data bit by bit. This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction and also allows indirect bit specification using the L register. continued processing. Fig. 4-63
Address Bit Symbol 3 FC3H 2 1 0 3
In this case, only by incrementing or
decrementing the L register in a program loop, the bit to be manipulated can be sequentially shifted for
Format of the Bit Sequential Buffer
FC2H 2 1 0 3 FC1H 2 1 0 3 FC0H 2 1 0
BSB3
BSB2
BSB1
BSB0
L register
L=F
L=C L=B
L=8 L=7
L=4 L=3 DECS L
L=0
INCS L
Remark In pmem.@L addressing, bit specification is shifted according to the L register. Data can also be manipulated using direct addressing. The buffer can be used for applications such as continuous 1-bit data input or output operations by combining direct 1-bit, 4-bit, and 8-bit addressing with pmem.@L addressing. In 8-bit manipulation, the higher eight bits or lower eight bits can be manipulated by specifying BSB0 or BSB2. Example The 16-bit data of BUFF1 and BUFF2 are output from bit 0 of port 3 in serial mode. Program example CLR1 MOV MOV MOV MOV MOV LOOP0: SKT BR NOP SET1 BR LOOP1: CLR1 NOP NOP LOOP2: INCS BR RET L LOOP0 ; L L+1 PORT3.0 LOOP2 PORT3.0 ; Clear bit 0 of port 3 ; Dummy (timing adjustment) MBE XA, BUFF1 BSB0, XA XA, BUFF2 BSB2, XA L, #0 BSB0, @L LOOP1 ; Dummy (timing adjustment) ; Set bit 0 of port 3 ; Test specified BSB bit ; Set BSB2, 3 ; Set BSB0, 1
124
PD75517(A)
5. INTERRUPT FUNCTION
The PD75517(A) has nine interrupt sources and can handle multiple interrupts with a priority. The PD75517(A) is also provided with two features for accepting testable interrupts. Table 5-1 Interrupt Sources
Interrupt source INTBT (Reference time interval signal from basic interval timer) (Detection of both rising and falling edges) (Rising/falling edge detection specification)
In/out In
PriorityNote 1 1
Vectored interrupt request signal (vector table address) VRQ1 (0002H)
INT4 INT0 INT1 INTCSI0 INTT0
Out Out Out 2 3 4 5 VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ5 (000AH)
(Serial data transfer completion signal) (Match signal between programmable timer/ counter count register and modulo register) (Match signal from timer/pulse generator) (Rising edge detection for an INT2 pin input signal, or falling edge detection for either of KR0 to KR7 pin input signals)Note 2 (Signal from clock timer)
In In
INTTPG INT2
In Out
6
VRQ6 (000CH)
Testable input signal (Sets IRQ2 and IRQW.)
INTW
In
Notes 1. The priority is used when two or more interrupt requests are issued at a time. 2. See (3) in Section 5.2 for details on INT2. The following functions are provided for the interrupt control circuit of the PD75517(A). (a) Vectored interrupt function under hardware control which can determine whether to accept an interrupt by an interrupt enable flag (IExxx) and the interrupt master enable flag (IME) (b) Any interrupt start address can be set. (c) Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS) (d) Test function of an interrupt request flag (IRQxxx) (The software can confirm that an interrupt occurred.) (e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.) 5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT The interrupt control circuit of the PD75517(A) is configured as shown in Fig. 5-1. Each hardware item is mapped in the data memory space.
125
126
2 IM2 2 IM1 2 IM0 INT BT INT4 /P00 INT0 /P10 INT1 /P11
Note
Fig. 5-1 Block Diagram of Interrupt Control Circuit
Internal bus 4 (IME) Interrupt enable flag (IExxx) IPS 2 IST
IRQBT VRQn
Decoder
Both-edge detection circuit Edge detection circuit Edge detection circuit INTCSI0
IRQ4
IRQ0
IRQ1 Vector table address generator
IRQCSI0
Priority control circuit
INTT0
IRQT0
INTTPG
IRQTPG
INTW INT2 /P12 Rising edge detection circuit Falling edge detection circuit
IRQW
Selector
IRQ2
Standby release signal
KR0/P60 KR7/P73
PD75517(A)
IM2 Note Noise eliminator
PD75517(A)
5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT
(1) Interrupt request flag and interrupt enable flag The following nine interrupt request flags (IRQxxx) corresponding to the interrupt sources are available. INT0 interrupt request flag (IRQ0) INT1 interrupt request flag (IRQ1) INT2 interrupt request flag (IRQ2) INT4 interrupt request flag (IRQ4) BT interrupt request flag (IRQBT) The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to 0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation varies. (See Section 5.5.) The following nine interrupt enable flags (IExxx) corresponding to the interrupt request flags are available. INT0 interrupt enable flag (IE0) INT1 interrupt enable flag (IE1) INT2 interrupt enable flag (IE2) INT4 interrupt enable flag (IE4) BT interrupt enable flag (IEBT) When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag corresponding to that interrupt request flag disables the interrupt. When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested interrupt, a vectored interrupt request (VRQn) is issued. This signal is also used for releasing the standby mode. The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated with EI IExxx and DI IExxx instructions. An SKTCLR instruction is normally used to test an interrupt request flag. Example EI DI IE0 IE1 ;Enables INT0. ;Disables INT1. Serial interface enable flag (IECSI0) Timer/event counter 0 interrupt enable flag (IET0) Timer/pulse generator interrupt enable flag (IETPG) Clock timer interrupt enable flag (IEW) Serial interface interrupt request flag (IRQCSI0) Timer/event counter 0 interrupt request flag (IRQT0) Timer/pulse generator interrupt request flag (IRQTPG) Clock timer interrupt request flag (IRQW)
SKTCLR IRQCSI0 ; Skips and clears the interrupt request flag if IRQCSI0 is 1. When an interrupt request flag is set with an instruction, a vectored interrupt is executed irrespective of whether an interrupt occurs. When a RESET signal is generated, an interrupt request flag and its corresponding interrupt enable flag are cleared and all interrupts are disabled.
127
PD75517(A)
Table 5-2 Set Signals of Interrupt Request Flags
Interrupt request flag IRQBT IRQ4 IRQ0
Set signal of interrupt request flag Set by a reference time interval signal from the basic interval timer. Set by a detected rising or falling edge of an INT4/P00 pin input signal. Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified by the INT0 mode register (IM0). Set by a detected edge of an INT1/P11 pin input signal. by the INT1 mode register (IM1). The detection edge is specified
Interrupt enable flag IEBT IE4 IE0
IRQ1
IE1
IRQCSI0 IRQT0 IRQTPG IRQW IRQ2
Set by a serial data transfer completion signal for the serial interface. Set by a match signal from timer/event counter 0. Set by a match signal from the timer/pulse generator. Set by a signal from the clock timer. Set by a detected rising edge of an INT2/P12 pin input signal, or a detected falling edge of one of a KR0/P60-KR7/P73 pin input signals.
IECSI0 IET0 IETPG IEW IE2
(2) Configurations of INT0, INT1, and INT4 pins (a) As shown in Fig. 5-2 (a), INT0 is configured as an external interrupt pin that enables detection edge selection. In addition, the INT0 pin is provided with a noise elimination function using a sampling clock. The noise eliminator eliminates pulses narrower than two-sampling-clock-cycle pulses (2tCYNote or 128/ fX) as noise and accepts pulses wider than as interrupt signals. INT0 has two sampling clocks and fX/64, either of which can be selected according to bit 3 (IM03) of the edge detection mode register (IM0). Bits 0 and 1 (IM00 and IM01) of the edge detection mode register (IM0) are used to select a detection edge. Fig. 5-3 (a) shows the format of IM0. A 4-bit memory manipulation instruction is used to set IM0. A RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected. Note tCY represents a cycle time. Cautions 1. Since the INT0 input is sampled with a clock, INT0 does not operate in a standby mode. 2. Input a pulse wider than two sampling clock cycles to the INT0/P10 pin. Otherwise, the pulse is suppressed as noise by the noise eliminator when the pin is used as a port. (b) As shown in Fig. 5-2 (b), INT1 is configured as an external interrupt pin that enables detection edge selection. The edge detection mode register (IM1) is used to select a detection edge. Fig. 5-3 (b) shows the format of IM1. A 4-bit memory manipulation instruction is used to set IM1. A RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected. (c) As shown in Fig. 5-2 (c), INT4 is configured as an external interrupt pin that enables detection of both rising and falling edges.
128
PD75517(A)
Fig. 5-2 Configurations of INT0, INT1, and INT4 Pins (a) Configuration of INT0
INT0 INT0/P10 Noise elimination circuit Edge detection circuit IM01,IM00 2 IRQ0 set signal
Selector
IM03
IM0 fx/64 Input buffer 4 Internal bus
Detection edge specification Sampling clock selection
(b) Configuration of INT1
INT1 INT1/P11 Edge detection circuit IM10 Detection edge specification IRQ1 set signal
IM1 Input buffer
4 Internal bus
(c) Configuration of INT4
INT4 INT4/P00 Both-edge detection circuit IRQ4 set signal
Input buffer
Internal bus
129
PD75517(A)
Fig. 5-3 Format of Edge Detection Mode Registers (a) INT0 edge detection mode register (IM0)
Address FB4H Symbol IM0
3 IM03
2 0
1 IM01
0 IM00
Detection edge specification 0 0 1 1 0 1 0 1 Specifies rising edge. Specifies falling edge. Specifies both rising and falling edges. Ignored (interrupt request flag is not set.)
Sampling clock 0 1 fX/64 (at 10.7s/6.0 MHz, or 15.3 s/4.19 MHz)
(b) INT1 edge detection mode register (IM1)
FB5H
0
0
0
IM10
IM1
0 1
Specifies rising edge. Specifies falling edge.
(c) INT2 edge detection mode register (IM2)
FB6H
0
0
IM21
IM20
IM2
IM21 0 0 1 1
IM20 0 1 0 1
INT2 interrupt source Specifies rising edge of INT2 pin input.
Interrupt input pin INT2 (1) KR4 - KR7 (4)
Specifies falling edge of any of KRx pin inputs.
KR2 - KR7 (6) KR0 - KR7 (8)
Caution Since changing or setting the edge detection mode register may set an interrupt request flag, disable the interrupts before changing the edge detection mode register. Then clear the interrupt request flag with a CLR1 instruction and enable the interrupts. When fX/64 is selected as a sampling clock pulse in changing IM0, wait for 16 machine cycles after changing the mode register and clear the interrupt request flag.
130
PD75517(A)
(3) Configuration of INT2 and KR0 to KR7 (key interrupt) pins Fig. 5-4 shows the configuration of INT2 and KR0 to KR7. IRQ2 is set in one of the following modes with the edge detection mode register (IM2): (a) Detection of a rising edge of the INT2 pin input When a rising edge of the INT2 pin input is detected, IRQ2 is set. (b) Detection of a falling edge of one of the KR0 to KR7 pin inputs (key interrupt) One of the pins KR0 to KR7 is selected to be used for interrupt input with the edge detection mode register (IM2). When a falling edge of one of input signals applied to the selected pin is detected, IRQ2 is set. Example If KR4 to KR7 are selected, and the level of signals input to KR4 to KR7 are all high, a falling edge appearing on any one of these inputs sets IRQ2. Caution If any of the selected pins has been input a low-level signal, a falling edge appearing on another pin does not set IRQ2. Fig. 5-3 (c) shows the format of IM2. A 4-bit memory manipulation instruction is used to set IM2. A RESET signal occurrence clears all bits to 0, and a rising edge is selected for INT2.
131
132
Fig. 5-4 Configuration of INT2 and KR0 to KR7
INT2/P12 Rising edge detection circuit KR7/P73 KR6/P72 KR5/P71 KR4/P70 KR3/P63 KR2/P62 KR1/P61 KR0/P60 Selector INT2 (IRQ2 set signal) Falling edge detection circuit Input buffer IM2 4 Internal bus
PD75517(A)
PD75517(A)
(4) Interrupt priority specification register (IPS) The interrupt priority specification register specifies an interrupt with a higher priority from multiple interrupts using the low-order three bits. Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts. The IPS is set with a 4-bit memory manipulation instruction. Bit 3 is set with an EI instruction and reset with a DI instruction. When a RESET signal is generated, all bits are cleared. Caution Disable interrupts before setting the IPS. Fig. 5-5 Interrupt Priority Specification Register
Address 3 FB2H IPS3 2 IPS2 1 IPS1 0 IPS0
Symbol IPS
High-order interrupt selection 0 0 0 0 0 1 All low-order interrupt VRQ1 (INTBT/INT4) The listed vectored interrupts are treated as high-order interrupts.
0
1
0
VRQ2 (INT0)
0
1
1
VRQ3 (INT1)
1
0
0
VRQ4 (INTCSI0)
1
0
1
VRQ5 (INTT0)
1 1
1 1
0 1
VRQ6 (INTTPG) This status is disabled.
Interrupt master enable flag (IME) 0 All interrupts are disabled and no vectored interrupt is activated. The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling/disabling.
1
133
PD75517(A)
5.3 INTERRUPT SEQUENCE
The following flowchart shows the sequence of an interrupt.
Interrupt (INTxxx) occurrence
IRQxxx setting
NO IExxx set? YES Corresponding VRQn occurrence Hold until IExxx is set.
IME = 1 YES Is VRQn high-order interrupt? YES
Note 1
NO
Hold until IME is set. Hold until processing being executed is finished
NO
NO
Note 1
NO
IST1, 0 = 00 or 01 YES
IST1, 0 = 00 YES
If two or more VRQns occur, select one VRQn according to Table 5-1. Selected VRQn Remaining VRQns
Save contents of PC and PSW in stack memory and set dataNote 2 in vector table corresponding to activated VRQn to PC, RBE, and MBE.
Change contents of IST0 and IST1 from 00 to 01 or from 01 to 10.
Reset accepted IRQxxx. See Section 5.5 when those interrupt sources share vector address.
Jump to the start address for processing the interrupt service program.
Notes 1. IST1 and IST0: Interrupt status flags (Bits 3 and 2 of PSW. See Table 5-3.) 2. Each vector table must store the start address of the interrupt service program and the set values of the MBE and RBE at the start of an interrupt.
134
PD75517(A)
5.4 MULTIPLE INTERRUPT PROCESSING CONTROL
The PD75517(A) can handle multiple interrupts by either of the following methods. (1) Multiple interrupt processing by a high-order interrupt In this method, the PD75517(A) selects an interrupt source among multiple interrupt sources, enabling double interrupt processing. That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order interrupt) are enabled only when the status is 0. (See Fig. 5-6 and Table 5-3.) Fig. 5-6 Multiple Interrupt Processing by a High-Order Interrupt
Normal processing (Status 0) Interrupt is disabled. IPS setting Interrupt is enabled.
Low- or high-order interrupt processing (Status 1)
High-order interrupt processing (Status 2)
Low- or high-order interrupt occurrence
High-order interrupt occurrence
Table 5-3 Interrupt Processing Statuses of IST1 and IST0
After acceptance
IST1 0
IST0 0
Processing status Status 0
CPU operation Is processing the normal program. Is processing a low- or highorder interrupt. Is processing a high-order interrupt.
Interrupts that can be accepted IST1 All 0 IST0 1
0
1
Status 1
Only high-order interrupts
1
0
1 1
0 1
Status 2
No
-
-
This status is disabled.
IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed, the former values of IST0 and IST1 are returned.
135
PD75517(A)
(2) Multiple interrupt processing by changing the interrupt status flags As shown in Table 5-3, changing the interrupt status flags with the program causes multiple interrupts to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status 0), multiple interrupt processing is enabled. This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed. When changing IST1 and IST0, interrupts must be disabled beforehand with a DI instruction. Fig. 5-7 Multiple Interrupt Processing by Changing the Interrupt Status Flags
Normal processing (status 0)
Single interrupt
Multiple interrupts
Interrupt is disabled. IPS setting Interrupt is enabled. Interrupt is disabled. Modification of IST Interrupt is enabled. Low- or high-order interrupt occurrence
Status 1
Low- or high-order interrupt occurrence
Status 0 Status 1
Status 0
136
PD75517(A)
5.5 VECTOR ADDRESS SHARE INTERRUPT PROCESSING
Since interrupt sources INTBT and INT4 share the vector table, the following two cases must be considered. (1) When using only one interrupt source The interrupt enable flag corresponding to the required interrupt source of the two interrupt sources sharing the vector table is set and the other interrupt enable flag is cleared. In this case, the enabled interrupt source (IExxx = 1) issues an interrupt request. If this request is accepted, the corresponding interrupt request flag is reset. (2) When using both interrupt sources The interrupt enable flags corresponding to the two interrupt sources are set. In this case, the logical and of the interrupt request flags corresponding to the two interrupt sources is an interrupt request. Even if one or both of the interrupt request flags are set and an interrupt request is accepted, neither of the interrupt request flags is reset. The interrupt service routine must therefore judge which interrupt source caused an interrupt. This is done by executing a DI instruction at the beginning of the interrupt service routine and checking the interrupt request flags with an SKTCLR instruction. Remark When only one interrupt is enabled, its interrupt source can be clearly identified, so that the interrupt request flag is reset by hardware at acceptance of the interrupt. However, when both interrupts are enabled, the interrupt source cannot be identified, so that the interrupt request flags cannot be reset by hardware. For this reason, the interrupt request flags are checked by software to determine the interrupt source.
137
PD75517(A)
6. STANDBY FUNCTION
To reduce the power consumption when the program is in the wait state, the PD75517(A) has two standby modes, STOP and HALT. 6.1 SETTING OF STANDBY MODES AND OPERATION STATUSES Table 6-1 Operation Statuses in the Standby Mode
STOP mode Instruction for setting System clock at setting STOP instruction This mode can be set only when the main system clock is used.
HALT mode HALT instruction This mode can be set when either the main system clock or the subsystem clock is used. Only CPU clock is stopped (with oscillation continued). Operation is continued (to set IRQBT at reference time intervals). Operation is possible only when the main system clock operates or external SCK0 is used. Operation is possible only when the main system clock operates. Operation is possible only when the main system clock operates. Operation is possible.
Operation status
Clock generator
Only the main system clock is stopped.
Basic interval timer Serial interface (Channel 0)
Operation is stopped.
Operation is possible only when external SCK0 input is selected for the serial clock.
Serial interface (Channel 1) Timer/event counter Watch timer
Operation is possible only when external SCK1 input is selected for the serial clock. Operation is possible only when TI0 pin input is selected for the count clock. Operation is possible only when fXT is selected for the count clock. Operation is stopped.
A/D converter
Operation is possible only when the main system clock operates. Operation is possible only when the main system clock operates.
Timer/pulse generator External interrupt CPU Release signal
Operation is stopped.
INT0 is disabled. INT1, INT2, and INT4 are enabled. Operation is stopped. Interrupt request signals transmitted from hardware, which are enabled by interrupt enable flags, or RESET input.
138
PD75517(A)
A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode. (A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.) A STOP instruction or HALT instruction must always be followed by an NOP instruction. When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from the time when PCC is rewritten to the time when the CPU clock signal is changed. When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode is released, it is necessary to rewrite PCC and set the standby mode after the number of machine cycles required to change the CPU clock pulse elapses. In a standby mode, the contents of all registers and data memory that are stopped during the standby mode, including general registers, flags, mode registers, and output latches, are retained. Cautions 1. When the STOP mode is set, the X1 input is internally connected to GND (GND potential) to suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot be used with a system that uses an external clock. 2. Reset all the interrupt request flags before setting the standby mode. If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set (see Fig. 5-1). When the STOP mode is set, however, the PD75517(A) enters the HALT mode immediately after the STOP instruction is executed, then returns to the operation mode after the wait time specified by the BTM register has elapsed. 6.2 RELEASE OF THE STANDBY MODES
The STOP mode and HALT mode are released by a RESET input or the generation of an interrupt request signal that is enabled with the interrupt enable flag. Fig. 6-1 shows how the STOP and HALT modes are released.
139
PD75517(A)
Fig. 6-1 Standby Mode Release Operation (a) Release of the STOP mode by RESET input
STOP instruction RESET signal Operating mode Oscillation Operating mode
Wait approximately 21.8 ms/6.0 MHz
Note
STOP mode No oscillation
HALT mode Oscillation
Clock
Note
A wait time is 31.3 ms when operating at 4.19 MHz.
(b) Release of the STOP mode by the occurrence of an interrupt
STOP instruction Standby release signal Operating mode Oscillation STOP mode No oscillation HALT mode Oscillation Operating mode Wait (Time set by BTM)
Clock
Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted. (c) Release of the HALT mode by RESET input
HALT instruction RESET signal Operating mode Operating mode Wait approximately 21.8 ms/6.0 MHz
Note
HALT mode Oscillation
Clock
Note
A wait time is 31.3 ms when operating at 4.19 MHz.
(d) Release of the HALT mode by the occurrence of an interrupt
HALT instruction Standby release signal Operating mode HALT mode Oscillation Operating mode
Clock
Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted.
140
PD75517(A)
The wait times used when the STOP mode is released do not include a time (a in Fig. 6-2) required before clock generation is started following the release of the STOP mode, regardless of whether the STOP mode is released by RESET signal input or the generation of an interrupt. Fig. 6-2 Start of Clock Generation
STOP mode release Wave-form at the X1 pin
a GND
When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by BTM. (See Table 6-2.) Table 6-2 Selection of a Wait Time with BTM (When fX = 4.19 MHz)
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1
Wait timeNote. ( ) indicates the value for fX = 6.0 MHz
Approx. 220/fX (Approx. 175 ms) Approx. 217/fX (Approx. 21.8 ms) Approx. 215/fX (Approx. 5.46 ms) Approx. 213/fX (Approx. 1.37 ms) Use prohibited
Other than above
(When fX = 4.19 MHz)
BTM3 - - - - BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 1 1 1 1
Wait timeNote. ( ) indicates the value for fX = 4.19 MHz
Approx. 220/fX (Approx. 250 ms) Approx. 217/fX (Approx. 31.3 ms) Approx. 215/fX (Approx. 7.82 ms) Approx. 213/fX (Approx. 1.95 ms) Use prohibited
Other than above
Note This time does not include the time from the release of the STOP mode to the start of oscillation. 6.3 OPERATION AFTER A STANDBY MODE IS RELEASED
(1) If a standby mode is released by a RESET input, normal reset operation is performed. (2) If a standby mode is released by the occurrence of an interrupt request, the interrupt master enable flag (IME) determines whether to perform a vectored interrupt when the CPU resumes instruction execution. (a) When IME = 0 After the standby mode is released, execution of an instruction is restarted immediately after the instruction which set the standby mode. The interrupt request flag is held. (b) When IME = 1 After the standby mode is released, two instructions are executed, then a vectored interrupt is caused. However, when the standby mode is released by INTW or INT2 (input of a testable signal), no vectored interrupt is caused and the same processing as (a) above is performed.
141
PD75517(A)
7. RESET FUNCTION
The PD75517(A) is reset by RESET signal input. When reset, the hardware is initialized as indicated in Table 7-1. Fig. 7-1 shows the timing of reset operation. Fig. 7-1 Reset Operation by RESET Input
Wait
(approximately 21.8 ms/6.0 MHz)Note
RESET input
Operation mode or standby mode
HALT mode
Operation mode
Internal reset operation
Note A wait time is 31.3 ms when operating at 4.19 MHz. Table 7-1 Statuses of the Hardware after a Reset (1/2)
Hardware Program counter (PC) RESET input in a standby mode
Low-order 6 bits at address 0000H in program memory are set in PC bits 13 to 8, and the data at address 0001H are set in PC bits 7 to 0.
RESET input during operation
Low-order 6 bits at address 0000H in program memory are set in PC bits 13 to 8, and the data at address 0001H are set in PC bits 7 to 0.
PSW
Carry flag (CY) Skip flags (SK0 to SK2) Interrupt status flags (IST0, IST1) Bank enable flags (MBE, RBE)
Held 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. HeldNote Held 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0, 0 Held 0 0
Undefined 0 0 Bit 6 at address 0000H in program memory is set in RBE, and bit 7 is set in MBE. Undefined Undefined 0, 0 Undefined Undefined Undefined 0 0 FFH 0 0, 0 Held 0 0
Data memory (RAM) General registers (X, A, H, L, D, E, B, C) Bank select register (MBS, RBS) Stack pointer (SP) Stack bank select register (SBS) Basic interval timer Timer/event counter Counter (BT) Mode register (BTM) Counter (T0) Modulo register (TMOD0) Mode register (TM0) TOE0, TOUT F/F Timer/pulse generator Watch timer Modulo registers (MODH, MODL) Mode register (TPGM) Mode register (WM)
Note RESET signal input causes data at addresses 0F8H-0FDH in data memory to be undefined.
142
PD75517(A)
Table 7-1 Statuses of the Hardware after a Reset (2/2)
Hardware Serial bus inter- Shift register 0 (SIO0) face Operation mode register 0 (CSIM0) (Channel 0) SBI control register (SBIC) Slave address register (SVA) P01/SCK0 output latch A/D converter Mode register (ADM), EOC SA register Clock genera- Processor clock control register tor, clock out- (PCC) put circuit System clock control register (SCC) Clock output mode register (CLOM) Serial interface Shift register (SIO1) (Channel 1) Operation mode register 1 (CSIM1) Serial transfer end flag (EOT) Interrupt Interrupt request flag (IRQxxx) Interrupt enable flag (IExxx) Interrupt master enable flag (IME) INT0, INT1 and INT2 mode registers (IM0, IM1, IM2) Digital ports Output buffer Output latch I/O mode registers (PMGA, PMGB, PMGC) Pull-up resistor specification register (POGA) Bit sequential buffers (BSB0 to BSB3) RESET input in a standby mode Held 0 0 Held 1 04H (EOC = 1) Undefined 0 RESET input during operation Undefined 0 0 Undefined 1 04H (EOC = 1) Undefined 0
0 0 Held 0 0 Reset (0) 0 0 0, 0, 0
0 0 Undefined 0 0 Reset (0) 0 0 0, 0, 0
Off Clear (0) 0
Off Clear (0) 0
0
0
Held
Undefined
143
PD75517(A)
8. INSTRUCTION SET
8.1
PD75517(A) INSTRUCTIONS
(1) GETI instruction The GETI instruction references a two-byte table in the program memory and performs the following three types of operations. This 1-byte instruction is very useful in reducing the number of program steps. (a) A subroutine call is made to all the spaces, regarding data in a table as the call address of a call instruction. (b) A branch is made to all the spaces, regarding data in a table as the branch address of a branch instruction. (c) Data in a table is executed as a double-byte or 1-byte instruction. The tables to be referenced by a GETI instruction are located at addresses 0020H to 007FH in the program memory. That is, data can be set in up to 48 tables. When describing a table address as an operand, describe an even address. Cautions 1. A two-byte instruction which can be referenced by a GETI instruction must be a twomachine-cycle instruction. (Except for the BRCB and CALLF instructions) 2. When referencing two 1-byte instructions with a GETI instruction, only the combinations listed in the table below are valid.
Instruction of first byte MOV A,@HL MOV @HL,A XCH A,@HL Instruction of second byte INCS DECS INCS DECS INCS INCS DECS INCS DECS INCS INCS DECS INCS DECS L L H H HL E E D D DE L L D D
MOV A,@DE XCH A,@DE
MOV A,@DL XCH A,@DL
3. Branch and subroutine instructions can be referenced by the GETI instruction only when their destination addresses are in the 16K-byte space (0000H to 3FFFH). A branch or subroutine instruction to an address from 4000H to 5F7FH cannot be referenced by the GETI instruction.
144
PD75517(A)
Since PC does not increment the counter during execution of a GETI instruction, control returns to the address next to the GETI instruction after the execution of the GETI instruction. When the instruction before a GETI instruction has the skip function, the GETI instruction is skipped in the same way as for other 1-byte instructions. When the instruction referenced by a GETI instruction has the skip function, the instructions after the GETI instruction are skipped. When a string effect instruction is referenced by a GETI instruction, the following results are obtained. * When the group of the string effect instruction before the GETI instruction is the same as that of the instruction referenced by the GETI instruction, the effect of the string effect instruction is canceled and the referenced instruction is not skipped. * When the group of the instruction after the GETI instruction is the same as that of the instruction referenced by the GETI instruction, the effect of the string effect instruction caused by the referenced instruction is valid and the instructions after the referenced instruction are skipped. (2) Bit manipulation instructions The PD75517(A) is provided with bit test instructions, bit transfer instructions, and bit Boolean instructions (AND, OR, and XOR) in addition to normal bit manipulation instructions (set instruction and clear instruction). Manipulation bits are specified by bit manipulation addressing. There are three types of bit manipulation addressing. The table below lists the bits manipulated by each addressing.
Addressing fmem.bit Specifiable peripheral hardware RBE/MBE/IST1, IST0/EOT IExxx/IRQxxx Port 0 to Port 15 pmem.@L BSB0 Ports 0, 4, 8, and 12 All the peripheral manipulatable) hardware Specifiable bit address range FB0H to FBFH
FF0H to FFFH FC0H to FFFH
@H+mem.bit
(bit- All the bits of the memory bank specified by MB (bit-manipulatable)
xxx: 0, 1, 2, 4, BT, T0, W, CSI0, TPG MB = MBE*MBS
145
PD75517(A)
(3) String effect instructions When two or more instructions in the same group (group A or B) are placed at two or more string effect addresses, the instruction placed at the start point of the string effect instructions is executed. After that, each string effect instruction is executed as an NOP instruction. Group A: MOV A, #n4, MOV XA, #n8 Group B: MOV HL, #n8 (4) Base conversion instruction The PD75517(A) is provided with base conversion instructions to convert the results of addition and subtraction of 4-bit data to a base-n number. When a base-m number is to be obtained, the following combinations of instructions are used for adjustment.
* For addition
ADDS A, #16-m ADDC A, @HL ADDS A, #m
* For subtraction SUBC A, @HL
ADDS A, #m The result of adding or subtracting the contents of the accumulator and the memory addressed by the HL register pair is converted to a base-m number. However, for subtraction, the complement of the obtained result (base-m number) is set in the accumulator. An overflow or underflow is reflected in the carry flag. (In the above combinations, the skip function of the ADDS A, #m instruction is prohibited.)
146
PD75517(A)
8.2 INSTRUCTION SET AND ITS OPERATION
(1) Representation format and description method of operands An operand is described in the operand field of each instruction according to the description method corresponding to the operand representation format of the instruction. Refer to the assembler specifications for details. When two or more elements are described in the description method field, select one of them. Uppercase letters, a plus sign (+), and a minus sign (-) are keywords, so they can be used without alteration. Specify an appropriate numeric value or label for immediate data.
Representation format reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr addr1 caddr faddr taddr PORTn IExxx RBn MBn
Description method X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or labelNote 2-bit immediate data or label FB0H-FBFH/FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label 0000H-3F7FH immediate data or label 0000H-5F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H-7FH immediate data (bit 0 = 0) or label PORT0-PORT15 IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG RB0-RB3 MB0, MB1, MB2, MB3, MB15
Note Only even addresses can be specified for 8-bit data processing.
147
PD75517(A)
(2) Legend A B C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE IME IPS RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : A register, 4-bit accumulator B register, 4-bit accumulator C register, 4-bit accumulator D register, 4-bit accumulator E register, 4-bit accumulator H register, 4-bit accumulator L register, 4-bit accumulator X register, 4-bit accumulator Register pair (XA), 8-bit accumulator Register pair (BC), 8-bit accumulator Register pair (DE), 8-bit accumulator Register pair (HL), 8-bit accumulator Extended register pair (XA') Extended register pair (BC') Extended register pair (DE') Extended register pair (HL') Program counter Stack pointer Carry flag, bit accumulator Program status word Memory bank enable flag Register bank enable flag Port n (n = 0 to 15) Interrupt master enable flag Interrupt priority specification register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address/bit delimiter Contents addressed by xx Hexadecimal data
PORTn:
IExxx :
148
PD75517(A)
(3) Explanation of the symbols in the addressing area field
*1
MB = MBE*MBS (MBS = 0, 1, 2, 3, or 15) MB = 0 MBE = 0: MB = 0 (00H-7FH) MB = 15 (80H-FFH) MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15) MB = 15, fmem = FB0H-FBFH or FF0H-FFFH MB = 15, pmem = FC0H-FFFH addr = 0000H-3F7FH addr = (Current PC) - 15 to (Current PC) - 1 or (Current PC) + 2 to (Current PC) + 16 caddr = 0000H-0FFFH 1000H-1FFFH 2000H-2FFFH 3000H-3FFFH 4000H-4FFFH 5000H-5F7FH faddr = 0000H-07FFH taddr = 0020H-007FH addr1 = 0000H-5F7FH (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 (PC14,13,12 = = = = = = 000B) 001B) 010B) 011B) 100B) 101B) or or or or or Program memory addressing Data memory addressing
*2 *3
*4
*5 *6 *7
*8
*9 *10 *11
Remarks 1. 2. 3. 4.
MB indicates an accessible memory bank. For *2, MB is always 0 irrespective of MBE and MBS. For *4 and *5, MB is always 15 irrespective of MBE and MBS. *6 to *11 indicate each addressable area.
(4) Explanation of the machine cycle column S represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. S assumes one of the following values: * When no skip operation is performed: * When a 3-byte instructionNote is skipped: Note Caution S=0 S=2
* When a 1-byte instruction or 2-byte instruction is skipped: S = 1
3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of the CPU clock, and three types of times are available for selection according to the PCC setting.
149
PD75517(A)
Instruction Mnemonic Transfer instruction MOV Operand A,#n4 reg1,#n4 XA,#n8 HL,#n8 rp2,#n8 A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL @HL,A @HL,XA A,mem XA,mem mem,A mem,XA A,reg XA,rp' reg1,A rp'1,XA XCH A,@HL A,@HL+ A,@HLA,@rpa1 XA,@HL A,mem XA,mem A,reg1 XA,rp' MOVT XA,@PCDE XA,@PCXA XA, @BCDENote XA, @BCXANote
Number Machine of bytes cycle
Operation A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC14-8+DE)ROM XA (PC14-8+XA)ROM XA (B2-0+CDE)ROM XA (B2-0+CXA)ROM
Addressing area
Skip condition String effect A
1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 1 1
1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 3 3
String effect A String effect B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
*11 *11
Note
Only lower three bits are valid in the B register.
150
PD75517(A)
Instruction Mnemonic Bit transfer instruction MOV1 Operand CY,fmem.bit CY,pmem.@L CY,@H+mem.bit fmem.bit,CY pmem.@L,CY @H+mem.bit,CY ADDS Arithmetic/logical instruction A,#n4 XA,#n8 A,@HL XA,rp' rp'1,XA ADDC A,@HL XA,rp' rp'1,XA SUBS A,@HL XA,rp' rp'1,XA SUBC A,@HL XA,rp' rp'1,XA AND A,#n4 A,@HL XA,rp' rp'1,XA OR A,#n4 A,@HL XA,rp' rp'1,XA XOR A,#n4 A,@HL XA,rp' rp'1,XA
Number Machine of bytes cycle
Operation CY (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) (fmem.bit) CY (pmem7-2+L3-2.bit(L1-0)) CY (H+mem3-0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A,CY A + (HL) + CY XA,CY XA + rp' + CY rp'1,CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A,CY A - (HL) - CY XA,CY XA - rp' - CY rp'1,CY rp'1 - XA - CY
Addressing area
Skip condition
2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
*4 *5 *1 *4 *5 *1 carry carry *1 carry carry carry *1
*1
borrow borrow borrow
*1
n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
AA
*1
*1
*1
151
PD75517(A)
Instruction Mnemonic Accumulator manipu- RORC lation instruction NOT Increment/ INCS decrement instruction A A reg rp1 @HL mem DECS reg rp' CompariSKE son instruction reg,#n4 @HL,#n4 A,@HL XA,@HL A,reg XA,rp' Carry flag SET1 manipulaCLR1 tion SKT instruction NOT1 CY CY CY CY Operand
Number Machine of bytes cycle
Operation CY A0,A3 CY, An-1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
Addressing area
Skip condition
1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
CY = 1
152
PD75517(A)
Instruction Mnemonic SET1 Memory bit manipulation instruction CLR1 Operand mem.bit fmem.bit pmem.@L @H+mem.bit mem.bit fmem.bit pmem.@L @H+mem.bit SKT mem.bit fmem.bit pmem.@L @H+mem.bit SKF mem.bit fmem.bit pmem.@L @H+mem.bit SKTCLR fmem.bit pmem.@L @H+mem.bit AND1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit OR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit XOR1 CY,fmem.bit CY,pmem.@L CY,@H+mem.bit BR Branch instruction $addr !addr PCDE PCXA BCDENote BCXANote BRA BRCB !addr1 !caddr 1 3 2 2 2 2 3 2 addr1
Number Machine of bytes cycle
Operation (mem.bit) 1 (fmem.bit) 1 (pmem7-2+L3-2.bit(L1-0)) 1 (H+mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2+L3-2.bit(L1-0)) 0 (H+mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2+L3-2.bit(L1-0)) = 1 Skip if (H+mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2+L3-2.bit(L1-0)) = 0 Skip if (H+mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
Addressing area
Skip condition
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 --
2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 --
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *11
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H+mem.bit) = 1
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H+mem.bit) = 0
(fmem.bit) = 1 (pmem.@L) = 1
(@H+mem.bit) = 1
Skip if (H+mem3-0.bit) = 1 and clear
(fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2+L3-2.bit(L1-0)) CY CY (H+mem3-0.bit)
CY CY PC14-0 addr1
(The assembler selects an appropriate instruction from the BR !addr, BRA !addr1, BRCB !caddr, and BR $addr instructions.)
2 3 3 3 3 3 3 2
PC14-0 addr PC14 0, PC13-0 addr PC14-0 PC14-8 + DE PC14-0 PC14-8 + XA PC14-0 B2-0 + CDE PC14-0 B2-0 + CXA PC14-0 addr1 PC14-0 PC14,13,12 + caddr11-0
*7 *6
*11 *11 *11 *8
Note
Only lower three bits are valid in the B register.
153
PD75517(A)
Instruction Mnemonic
Subroutine stack control instruction
Operand !addr
Number Machine of bytes cycle
Operation (SP-2) x,x,MBE,RBE (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 PC14 0, PC13-0 addr, SP SP - 6
Addressing area
Skip condition
CALL
3
4
*6
CALLA
!addr1
3
3
(SP-2) x,x,MBE,RBE (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 PC14-0 addr, SP SP - 6 (SP-2) x,x,MBE,RBE (SP-6)(SP-3)(SP-4) PC11-0 (SP-5) 0,PC14,PC13, PC12 PC14-0 0000 + faddr, SP SP - 6
*11
CALLF
!faddr
2
3
*9
RET
1
3
PC11-0 (SP)(SP+3)(SP+2) x,PC14,PC13,PC12 (SP+1) x,x,MBE,RBE (SP+4) SP SP + 6 PC11-0 (SP)(SP+3)(SP+2) x,PC14,PC13,PC12 (SP+1) x,x,MBE,RBE (SP+4) SP SP + 6 then skip unconditionally PC11-0 (SP)(SP+3)(SP+2) x,PC14,PC13,PC12 (SP+1) PSW (SP+4)(SP+5), SP SP + 6 (SP-1)(SP-2) rp, SP SP - 2 (SP-1) MBS, (SP-2) RBS, SP SP - 2 rp (SP+1)(SP), SP SP + 2 MBS (SP+1), RBS (SP), SP SP + 2 IME(IPS.3) 1 IExxx 1 IME(IPS.3) 0 IExxx 0 A PORTn (n=0-15) XA PORTn+1,PORTn (n=4,6) PORTn A (n=2-7,9-14) PORTn+1,PORTn XA (n=4,6) Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation Unconditionally
RETS
1
3+S
RETI
1
3
PUSH
rp BS
1 2
1 2
POP
rp BS
1 2
1 2
Interrupt control instruction
EI IExxx DI IExxx
2 2 2 2 2 2 2 2 2 2 1
2 2 2 2 2 2 2 2 2 2 1
I/O instruction
INNote
A,PORTn XA,PORTn
OUTNote
PORTn,A PORTn,XA
CPU control instruction
HALT STOP NOP
Note
MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.
154
PD75517(A)
Instruction Mnemonic Special instruction SEL Operand RBn MBn GETINote taddr
Number Machine of bytes cycle
Operation RBS n (n=0-3) MBS n (n=0,1,2,3,15) * For a TBR instruction PC13-0 (taddr)4-0 + (taddr+1) PC14 0 * For a TCALL instruction (SP-5)(SP-6)(SP-3)(SP-4) PC14-0 (SP-2) x,x,MBE,RBE PC13-0 (taddr)5-0 + (taddr+1) SP SP-6 PC14 0 * For an instruction other than TBR and TCALL (taddr)(taddr+1)
Addressing area
Skip condition
2 2 1
2 2 3
*10
4
3
Depends upon the referenced instruction.
Note
The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI instructions.
155
PD75517(A)
8.3 INSTRUCTION CODES OF EACH INSTRUCTION
(1) Explanations of the symbols for the instruction codes
R2 0 0 0 0 1 1 1 1
R1 0 0 1 1 0 0 1 1
R0 0 1 0 1 0 1 0 1
reg A X L H reg E D C B reg1
P2 0 0 0 0 1 1 1 1
P1 0 0 1 1 0 0 1 1
P0 0 1 0 1 0 1 0 1
reg-pair XA XA' HL HL' DE DE' BC BC' rp'
rp'1
Q2 0 0 0 1 1
Q1 0 1 1 0 0
Q0 1 0 1 0 1
addressing @HL @HL+ @HL- @DE @DL @rpa @rpa1
P2 0 0 1 1
P1 0 1 0 1
reg-pair XA HL DE rp2 BC rp1 rp
N5 0 0 0 0 0 0 0 1 1
N2 0 0 0 1 1 1 1 0 1
N1 0 1 1 0 0 1 1 0 1
N0 0 0 1 0 1 0 1 0 0
IExxx IEBT IEW IETPG IET0 IECSI0 IE0 IE2 IE4 IE1
In : Immediate data for n4 or n8 Dn: Immediate data for mem Bn: Immediate data for bit Nn: Immediate data for n or IExxx Tn : Immediate data for taddr x 1/2 An: Immediate data for the relative address distance (2 to 16) for the branch destination address minus one Sn: Immediate data for the ones complement of the relative address distance (15 to 1) for the branch destination address
156
PD75517(A)
(2) Bit manipulation addressing instruction codes *1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@L, and @H+mem.bit. The table below lists the second byte *2 of an instruction code corresponding to the above addressing.
Second byte of instruction code 1 1 pmem.@L @H+mem.bit 0 0 0 1 1 0 B1 B1 0 B1 B0 B0 0 B0 F3 F3 G3 D3 F2 F2 G2 D2 F1 F1 G1 D1 F0 F0 G0 D0
*1 fmem.bit
Accessible bits FB0H - FBFH manipulatable bits FF0H - FFFH manipulatable bits FC0H-FFFH manipulatable bits Manipulatable bits of accessible memory bank
Bn : Immediate data for bit Fn : Immediate data for fmem (Low-order four bits of address) Gn: Immediate data for pmem (Bits 2 to 5 of address) Dn : Immediate data for mem (Low-order four bits of address)
157
PD75517(A)
Instruction Transfer instruction Instruction code Mnemonic MOV Operand A, #n4 reg1, #n4 rp, #n8 A, @rpa XA, @HL @HL, A @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA XCH A, @rpa XA, @HL A, mem XA, mem A, reg1 XA, rp' MOVT XA, @PCDE XA, @PCXA XA, @BCDE XA, @BCXA
Bit MOV1 transfer instruction
B1 0 1 1 1 I3 I2 I1 I0 10011010 1 0 0 0 1 P2 P1 1 1 1 1 0 0 Q2 Q1 Q0 10101010 11101000 10101010 10100011 10100010 10010011 10010010 10011001 10101010 10011001 10101010 1 1 1 0 1 Q2 Q1 Q0 10101010 10110011 10110010 1 1 0 1 1 R2 R1 R0 10101010 11010100 11010000 11010101 11010001 10111101 10011011
B2
B3
I3 I2 I1 I0 1 R2 R1 R0 I7 I6 I5 I4 I3 I2 I1 I0
00011000
00010000 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0 0 1 1 1 1 R2 R1 R0 0 1 0 1 1 P2 P1 P0 0 1 1 1 0 R2 R1 R0 0 1 0 1 0 P2 P1 P0
00010001 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0
0 1 0 0 0 P2 P1 P0
CY, *1 *1 , CY
*2 *2
158
PD75517(A)
Instruction Instruction code Mnemonic Operand B1 A, #n4 XA, #n8 A, @HL XA, rp' rp'1, XA ADDC A, @HL XA, rp' rp'1, XA SUBS A, @HL XA, rp' rp'1, XA SUBC A, @HL XA, rp' rp'1, XA AND A, #n4 A, @HL XA, rp' rp'1, XA OR A, #n4 A, @HL XA, rp' rp'1, XA XOR A, #n4 A, @HL XA, rp' rp'1, XA
Accumulator manipulation instruction
B2
B3
Arithme- ADDS tic/logical instruction
0 1 1 0 I3 I2 I1 I0 10111001 11010010 10101010 10101010 10101001 10101010 10101010 10101000 10101010 10101010 10111000 10101010 10101010 10011001 10010000 10101010 10101010 10011001 10100000 10101010 10101010 10011001 10110000 10101010 10101010 10011000 10011001 01011111 1 0 1 1 1 P2 P1 P0 1 0 1 1 0 P2 P1 P0 1 0 1 0 1 P2 P1 P0 1 0 1 0 0 P2 P1 P0 0 1 0 1 I3 I2 I1 I0 1 0 0 1 1 P2 P1 P0 1 0 0 1 0 P2 P1 P0 0 1 0 0 I3 I2 I1 I0 1 1 1 1 1 P2 P1 P0 1 1 1 1 0 P2 P1 P0 0 0 1 1 I3 I2 I1 I0 1 1 1 0 1 P2 P1 P0 1 1 1 0 0 P2 P1 P0 1 1 0 1 1 P2 P1 P0 1 1 0 1 0 P2 P1 P0 1 1 0 0 1 P2 P1 P0 1 1 0 0 0 P2 P1 P0 I7 I6 I5 I4 I3 I2 I1 I0
RORC NOT
A A
159
PD75517(A)
Instruction Increment/ decrement instruction Instruction code B1 INCS reg rp1 @HL mem DECS reg rp' Comparison instruction SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp' Carry flag manipulation instruction Memory bit manipulation instruction SET1 CLR1 SKT NOT1 SET1 CY CY CY CY mem.bit *1 CLR1 mem.bit *1 SKT mem.bit *1 SKF mem.bit *1 SKTCLR AND1 OR1 XOR1 *1 CY, *1 CY, *1 CY, *1 1 1 0 0 0 R2 R1 R0 1 0 0 0 1 P2 P1 P0 10011001 10000010 1 1 0 0 1 R2 R1 R0 10101010 10011010 10011001 10000000 10101010 10011001 10101010 11100111 11100110 11010111 11010110 1 0 B1 B0 0 1 0 1 10011101 1 0 B1 B0 0 1 0 0 10011100 1 0 B1 B0 0 1 1 1 10111111 1 0 B1 B0 0 1 1 0 10111110 10011111 10101100 10101110 10111100 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 D7 D6 D5 D4 D3 D2 D1 D0 *2 *2 *2 *2 *2 00011001 0 0 0 0 1 R2 R1 R0 0 1 0 0 1 P2 P1 P0 0 1 1 0 1 P2 P1 P0 I3 I2 I1 I0 0 R2 R1 R0 0 1 1 0 I3 I2 I1 I0 00000010 D7 D6 D5 D4 D3 D2 D1 D0 B2 B3
Mnemonic
Operand
160
PD75517(A)
Instruction Branch instruction Instruction code Mnemonic BR Operand B1 !addr $addr
(+16) to (+2) (-1) to (-15)
B2 00 addr
B3
10101011 0 0 0 0 A3 A2 A1 A0 1 1 1 1 S3 S2 S1 S0 10011001 10011001 10011001 10011001 10111010 0101 10101011 10111011 01000 11101110 11100000 11101111
PCDE PCXA BCDE BCXA BRA BRCB Subrou- CALL tine stack CALLA instrucCALLF tion RET RETS RETI PUSH rp BS POP rp BS I/O instruction IN A, PORTn XA, PORTn OUT PORTn, A PORTn, XA Interrupt control instruction EI IExxx DI IExxx CPU control instruction Special instruction HALT STOP NOP SEL RBn MBn GETI taddr !addr1 !caddr !addr !addr1 !faddr
00000100 00000000 00000101 00000001 0 caddr 01 0 faddr addr addr1 addr1
0 1 0 0 1 P2 P1 1 10011001 0 1 0 0 1 P2 P1 0 10011001 10100011 10100010 10010011 10010010 10011101 10011101 10011100 10011100 10011101 10011101 01100000 10011001 10011001 0 0 T5 T4 T3 T2 T1 T0 0 0 1 0 0 0 N1 N0 0 0 0 1 N3 N2 N1 N0 00000110 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 1 1 1 1 N3 N2 N1 N0 10110010 1 0 N5 1 1 N2 N1 N0 10110010 1 0 N5 1 1 N2 N1 N0 10100011 10110011 00000111
161
PD75517(A)
9. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Ports other than ports 4, 5, and 12 to 14 Ports 4, 5, Built-in pull-up resistor and 12 to Open drain 14 Conditions Rated value -0.3 to +7.0 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3 Each pin Total of all pins IOLNote Each pin Peak value rms Total of all pins of ports 0, 2, 3, and 4 Total of all pins of ports 5 to 11 Peak value rms Peak value rms Total of all pins of ports 12 to 14 Operating temperature Storage temperature Topt Peak value rms -15 -30 30 15 100 60 100 60 40 25 -40 to +85 Unit V V V V V mA mA mA mA mA mA mA mA mA mA C
Output voltage High-level output current Low-level output current
VO IOH
Tstg
-65 to +150
C
Note Calculate rms with [rms] = [peak value] x duty. OPERATING SUPPLY VOLTAGE
Parameter A/D converter Supply voltage Ambient temperature Timer/pulse generator Other circuits Supply voltage Ambient temperature Supply voltage Ambient temperature Symbol VDD Ta VDD Ta VDD Ta Min. 2.7 -40 4.5 -40 2.7 -40 Max. 6.0 +85 6.0 +85 6.0 +85 Unit V C V C V C Conditions
162
PD75517(A)
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Ceramic resonator Recommended constant Parameter Oscillator frequency (fX) Note 1 Min. 1.0 Typ. Max. 6.2 Unit MHz Conditions VDD = oscillation voltage range After VDD reaches Min. of the oscillation voltage range
X1
X2
C1
C2
Oscillation settling timeNote 2 Oscillator frequency (fX) Note 1 1.0 4.19
4
ms
Crystal resonator
6.2
MHz
X1
X2
C1
C2
Oscillation settling timeNote 2 X1 input frequency (fX) Note 1 X1 input high/low level width (tXH, tXL) 1.0
10 30 6.2
ms ms MHz
VDD = 4.5 to 6.0 V
External clock
X1
X2
81
500
ns
PD74HCU04
Notes 1. 2.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released.
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Crystal resonator Recommended constant
XT1 XT2 R C3 C4
Parameter Oscillator frequency (fXT) Note 1 Oscillation settling timeNote 2 XT1 input frequency (fXT) Note 1 XT1 input high/low level width (tXTH, tXTL)
Min. 32
Typ. 32.768
Max. 35
Unit kHz
Conditions
1.0
2 10
s s kHz
VDD = 4.5 to 6.0 V
External clock
32
100
XT1
XT2 Open
5
15
s
Notes 1. 2.
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of AC characteristics for the instruction execution time. The oscillation settling time means the time required for the oscillation to settle after VDD is applied or after the STOP mode is released.
CAPACITANCE (Ta = 25 C, VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Min. Typ. Max. 15 15 15 Unit pF pF pF Conditions f = 1 MHz 0 V for pins other than pins to be measured
163
PD75517(A)
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter High-level input voltage Symbol VIH1 VIH2 VIH3 Min. 0.7VDD 0.8VDD 0.7VDD 0.7VDD VIH4 Low-level input voltage VIL1 VIL2 VIL3 High-level output voltage Low-level output voltage VOH VDD - 0.5 0 0 0 VDD - 1.0 VDD - 0.5 VOL 0.4 2.0 Typ. Max. VDD VDD VDD 10 VDD 0.3VDD 0.2VDD 0.4 Unit V V V V V V V V V V V Conditions Ports 2, 3, and 9 to 11, P80, and P82 Ports 0, 1, 6, 7, and 15, P81, P83, and RESET Ports 4, 5, and 12 to 14 Built-in pull-up resistor Open drain
X1, X2, and XT1 Ports 2 to 5 and 9 to 14, P80, and P82 Ports 0, 1, 6, 7, and 15, P81, P83, and RESET X1, X2, and XT1 VDD = 4.5 to 6.0 V, IOH = -1 mA IOH = -100 A Ports 3, 4, and 5
VDD = 4.5 to 6.0 V, IOL = 15 mA
0.4 0.5 0.2VDD
V V V
VDD = 4.5 to 6.0 V, IOL = 1.6 mA IOL = 400 A SB0 and SB1 VI = VDD Open drain Pull-up resistor: 1 k or more Other than X1, X2, and XT1 X1, X2, and XT1 VI = 10 V Ports 4, 5, and 12 to 14 (open drain) Other than X1, X2, and XT1 X1, X2, and XT1 VO = VDD Other than ports 4, 5, and 12 to 14 Ports 4, 5, and 12 to 14 (open drain)
High-level input leakage current
ILIH1 ILIH2 ILIH3
3 20 20
A A A A A A A A
k k k k k
Low-level input leakage current High-level output leakage current
ILIL1 ILIL2 ILOH1
-3 -20 3
VI = 0 V
ILOH2
20
VO = 10 V
Low-level output leakage current Built-in pull-up resistor
ILOL
-3
VO = 0 V Ports 0, 1, 2, 3, 6, and VDD = 5.0 V 10 % 7 (excl. P00) VDD = 3.0 V 10 % VI = 0 V
Ports 4, 5, and 12 to 14
RU1
15 30
40
80 300
RU2
15 10
40
70 60
VDD = 5.0 V 10 % VDD = 3.0 V 10 % Port 9
VO = VDD - 2.0 V VO = 2 V
Built-in pull-down resistor
RD
20
70
140
164
PD75517(A)
Parameter Power supply current Note 1 Symbol IDD1 Min. Typ. 4.5 0.6 IDD2 700 250 IDD1 3 0.55 IDD2 600 200 IDD3 40 Max. 13.5 1.8 2100 750 9 1.5 1800 600 120 Unit mA mA 6.0 MHz crystal resonance C1 = C2 = 22 pF 4.19 MHz crystal resonance C1 = C2 = 22 pF 32.768 kHz crystal resonance Conditions Operation VDD = 5 V 10 %Note 2 mode VDD = 3 V 10 %Note 3 HALT mode VDD = 5 V 10 % VDD = 3 V 10 %
A A
mA mA
Operation VDD = 5 V 10 %Note 3 mode VDD = 3 V 10 %Note 3 HALT mode VDD = 5 V 10 % VDD = 3 V 10 %
A A A A
Operation VDD = 3 V 10 % mode HALT mode VDD = 3 V 10 %
IDD4
5
15
IDD5
0.5 0.3
20 10 5
A A A
XT1 = 0 V VDD = 5 V 10 % STOP mode VDD = 3 V 10 % Ta = 25 C
Notes 1. 2. 3.
This current excludes the current which flows through the built-in pull-up resistors. Value when the processor clock control register (PCC) is set to 0011 and the PD75517(A) is operated in the high-speed mode Value when the PCC is set to 0000 and the PD75517(A) is operated in the low-speed mode
165
PD75517(A)
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1) Basic operation
Parameter Cycle time (minimum instruction execution time)Note 1 TI0 input frequency Symbol tCY Min. 0.67 2.6 114 fTI 0 0 TI0 input high/low level width tTIH, tTIL 0.48 1.8
Note 2
Typ.
Max. 64 64
Unit
Conditions Operated by main system clock pulse VDD = 4.5 to 6.0 V
s s s
MHz kHz
122
125 1 275
Operated by subsystem clock pulse VDD = 4.5 to 6.0 V
s s s s s s
VDD = 4.5 to 6.0 V
Interrupt input high/low tINTH, level width tINTL
INT0 INT1, INT2, and INT4 KR0 to KR7
10 10
RESET low level width
tRSL
10
Notes 1. The cycle time (minimum instruction execution time) depends on the connected resonator frequency, the system clock control register (SCC), and the processor clock control register (PCC). The figure on the next page shows the cycle time tCY characteristics for the supply voltage VDD during main system clock operation. 2. This value becomes 2tCY or 128/fX according to the setting of the interrupt mode register (IM0).
Cycle time tCY [ s]
tCY vs VDD (When the main system clock is operating) 70 64 60 6 5 4 3 Guaranteed operating range
2
1
0.5 0 1 2 3 4 5 6 Supply voltage VDD [V]
166
PD75517(A)
(2) Serial transfer (a) Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Parameter SCK cycle time Symbol tKCY1 Min. 1600 1340 3800 2680 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) SCK SO output delay time tKL1 tKH1 tSIK1 tKCY/2 - 50 tKCY/2 - 150 150 Typ. Max. Unit ns ns ns ns ns ns ns Conditions VDD = 4.5 to 6.0 V fX = 4.19 MHz VDD = 4.5 to 6.0 V fX = 6.0 MHz fX = 4.19 MHz fX = 6.0 MHz VDD = 4.5 to 6.0 V
tKSI1
400
ns
tKSO1
250 1000
ns ns
RL = 1 k, CL = 100 pF Note
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively. (b) Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Parameter SCK cycle time Symbol tKCY2 Min. 800 3200 SCK high/low level width SI setup time (referred to SCK) SI hold time (referred to SCK) SCK SO output delay time tKL2 tKH2 tSIK2 400 1600 100 Typ. Max. Unit ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V
tKSI2
400
ns
tKSO2
300 1000
ns ns
RL = 1 k, CL = 100 pF Note
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
167
PD75517(A)
(c) SBI mode (SCK ... Internal clock output (master)):
Parameter SCK cycle time Symbol tKCY3 Min. 1600 1340 3800 2680 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) SCK SB0/SB1 output delay time SCK SB0/SB1 SB0/SB1 SCK SB0/SB1 low level width SB0/SB1 high level width tKL3 tKH3 tSIK3 tKCY/2 - 50 tKCY/2 - 150 150 Typ. Max. Unit ns ns ns ns ns ns ns Conditions VDD = 4.5 to 6.0 V fX = 4.19 MHz VDD = 4.5 to 6.0 V fX = 6.0 MHz fX = 4.19 MHz fX = 6.0 MHz VDD = 4.5 to 6.0 V
tKSI3
tKCY/2
ns
tKSO3
0 0
250 1000
ns ns ns ns ns
RL = 1 k , CL = 100 pFNote
VDD = 4.5 to 6.0 V
tKSB tSBK tSBL
tKCY tKCY tKCY
tSBH
tKCY
ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively. (d) SBI mode (SCK ... External clock input (slave)):
Parameter SCK cycle time Symbol tKCY4 Min. 800 3200 SCK high/low level width SB0/SB1 setup time (referred to SCK) SB0/SB1 hold time (referred to SCK) SCK SB0/SB1 output delay time SCK SB0/SB1 SB0/SB1 SCK SB0/SB1 low level width SB0/SB1 high level width tKL4 tKH4 tSIK4 400 1600 100 Typ. Max. Unit ns ns ns ns ns VDD = 4.5 to 6.0 V Conditions VDD = 4.5 to 6.0 V
tKSI4
tKCY/2
ns
tKSO4
0 0
300 1000
ns ns ns ns ns
RL = 1 k , CL = 100 pFNote
VDD = 4.5 to 6.0 V
tKSB tSBK tSBL
tKCY tKCY tKCY
tSBH
tKCY
ns
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
168
PD75517(A)
(3) A/D converter (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
Parameter Resolution
Absolute accuracyNote 1
Symbol
Min. 8
Typ. 8
Max. 8 1.5 2.0
Unit bit LSB
Conditions
2.5 V AVREF VDDNote 2 -10 Ta +85C -40 Ta < -10C
Conversion timeNote 3 Sampling timeNote 4 Analog input voltage Analog input impedance VAREF current
tCONV tSAMP VIAN RAN AVSS 1000
168/fX 44/fX AVREF
s s
V M
IAREF
1.0
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (1/2 LSB) 2. 2.5 V AVREF VDD ADM1 is set to 0 or 1 depending on the A/D converter reference voltage (AVREF) as follows:
2.5 V AVREF ADM1 = 0 ADM1 = 1 0.6VDD 0.65VDD VDD (2.7 to 6.0 V)
When 0.6 VDD AVREF 0.65 VDD, ADM1 can be set to either 0 or 1. 3. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1) (28.0 s: fX = 6.0 MHz, 40.1 s: fX = 4.19 MHz) 4. Time from the execution of a conversion start instruction till the end of sampling (7.33 s: fX = 6.0 MHz, 10.5 s: fX = 4.19 MHz)
169
PD75517(A)
AC Timing Measurement Points (Excluding X1 and XT1 Inputs)
0.8 VDD 0.2 VDD
Measurement point
0.8 VDD 0.2 VDD
Clock Timing
1/fX tXL tXH
VDD - 0.5 V X1 input 0.4 V
1/fXT tXTL tXTH
VDD - 0.5 V XT1 input 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
170
PD75517(A)
Serial Transfer Timing Three-wire serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI
Input data
tKSO1
SO
Output data
Two-wire serial I/O mode:
tKCY2 tKL2 tKH2
SCK tSIK2
tKSO2
tKSI2
SB0 and SB1
171
PD75517(A)
Serial Transfer Timing Bus release signal transfer:
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tSIK3, 4 tKSB tSBL tSBH tSBK tKSI3, 4
SB0 and SB1 tKSO3, 4
Command signal transfer:
tKCY3, 4 tKL3, 4 tKH3, 4
SCK tSIK3, 4 tKSB tSBK tKSI3, 4
SB0 and SB1 tKSO3, 4
Interrupt Input Timing
tINTL INT0, INT1, INT2 and INT4 KR0-KR7 tINTH
RESET Input Timing
tRSL
RESET
172
PD75517(A)
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE (Ta = -40 to +85 C)
Parameter Data hold supply voltage
Data hold supply currentNote 1
Symbol VDDDR IDDDR tSREL tWAIT
Min. 2.0 0
Typ. X 0.1
Max. 6.0 10
Unit V
Conditions
A s
VDDDR = 2.0 V
Release signal setting time Oscillation settling timeNote 2
2 /fX
Note 3
17
ms ms
Release by RESET Release by interrupt request
Notes 1. 2. 3.
Excluding the current which flows through the built-in pull-up resistors CPU operation stop time for preventing unstable operation at the beginning of oscillation This value depends on the settings of the basic interval timer mode register (BTM) shown below.
BTM3 -- -- -- -- BTM2 0 0 1 1 Wait time BTM1 0 1 0 1 BTM0 fX = 4.19 MHz 0 1 1 1 2 /fX (approx. 175 ms) 2 /fX (approx. 31.3 ms) 215/fX (approx. 7.82 ms) 213/fX (approx. 1.95 ms)
17 20 20
fX = 6.0 MHz 2 /fX (approx. 175 ms) 217/fX (approx. 21.8 ms) 215/fX (approx. 5.46 ms) 213/fX (approx. 1.37 ms)
Data Hold Timing (STOP Mode Release by RESET)
Internal reset operation HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode STOP mode Data hold mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (Interrupt request)
tWAIT
173
PD75517(A)
10. PACKAGE DIMENSIONS
PACKAGE DIMENSIONS OF 80-PIN PLASTIC QFP (14 x 20) (UNIT: mm)
A B
64 65
41 40
Detail of lead end
D
C
S
F
80
1
24
25
G
H
IM
J
K
P
N
L
M
Q
P80GF-80-3B9-2E
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 23.6
0.4
INCHES 0.9290.016 0.795 -0.008 0.551 -0.008 0.6930.016 0.039 0.031
+0.004 +0.009 +0.009
20.00.2 14.000.2 17.60.4 1.0 0.8 0.35 0.15 0.8 (T.P) 1.8
0.2 0.10
0.014 -0.005 0.006
0.031 (T.P.) 0.071 -0.009 0.031 -0.008 0.006 -0.003 0.006 0.106 0.0040.004 0.0040.004 0.119 MAX.
+0.008 +0.009 +0.004
0.80.2 0.15 -0.05 0.15 2.7 0.1
0.1 +0.10
0.10.1 3.0 MAX.
174
R
PD75517(A)
11. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering the PD75517(A). Please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. Table 11-1 Recommended Soldering Conditions
Part number Package Symbol WS60-162-1 IR30-162-1 VP15-162-1 Partial heating method
PD75517GF(A)-xxx-3B9
80-pin plastic QFP (14 mm x 20 mm)
Table 11-2 Soldering Conditions
Symbol WS60-162-1 Soldering process Wave soldering Soldering conditions Temperature in the soldering vessel: 260 C or less Soldering time: 10 seconds or less Number of soldering processes: 1 Exposure limitNote: 2 days (16 hours pre-baking is required at 125 C afterwards) Pre-heating temperature: 120 C max. (package surface temperature) Peak package's surface temperature: 230 C Reflow time: 30 seconds or below (at 210 C or more) Number of reflow processes: 1 Exposure limitNote: 2 days (16 hours pre-baking is required at 125 C afterwards) Peak package's surface temperature: 215 C Reflow time: 40 seconds or below (at 200 C or more) Number of reflow processes: 1 Exposure limitNote: 2 days (16 hours pre-baking is required at 125 C afterwards) Terminal temperature: 300 C or less Flow time: 3 seconds or less (one side per device)
IR30-162-1
Infrared ray reflow
VP15-162-1
VPS
Partial heating method
Partial heating method
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 C and relative humidity at 65 % or less. Caution Do not apply more than a single process at a time, except for "Partial heating method." For more details, refer to our document "SMT MANUAL" (IEI-1207).
175
PD75517(A)
APPENDIX A SERIES PRODUCT FUNCTIONS
Product Item ROM (bytes) RAM (x 4 bits) General register Machine Maincycle system clock Subsystem clock
Note 1
PD75517 PD75517(A)
24448 1024
PD75P518
32640 (PROM)
PD75516 PD75516(A)
16256 512
PD75P516
16256 (PROM)
(4 bits x 8 or 8 bits x 4) x 4 banks 0.67 s/1.33 s/2.67 s/10.7 s (at 6.0 MHz) 0.95 s/1.91 s/3.82 s/15.3 s (at 4.19 MHz) 0.95 s/1.91 s/15.3 s (at 4.19 MHz)
122 s (at 32.768 kHz) 64 16 (Shared with INT and SIO. Seven lines can be pulled up by software)
Total CMOS input CMOS I/O
I/O port
28 (LED direct driving and shared with SIO and PPO) * 16 lines can be pulled up by software. * Four lines can be pulled down by the mask option. 20 (Eight lines for driving LEDs. Withstand voltage is 10 V. 20 lines can be pulled up by the mask option.) 20 (Eight lines for driving LEDs. Withstand voltage is 9 V. 20 lines can be pulled up by the mask option.)
N-ch opendrain I/O A/D converter Operating voltage Timer/counter
* 8-bit resolution x 8 ch (successive approximation) VDD = 2.7 to 6.0 V 4 channels * * * * 2 channels * * * * * * VDD = 3.5 to 6.0 V
Timer/event counter Basic interval timer Timer/pulse generator (14-bit PWM output possible) Clock timer NEC standard serial bus interface (SBI)/three-wire SIO : One channel General synchronous serial interface (three-wire SIO) : One channel
Serial interface
Interrupt
Vectored interrupt: Seven sources (External: 3, Internal: 4) Test input: Two sources (External: 1, Internal: 1) Clock test flag is provided. Parallel-edge-sensitive flag for key scan input is provided.
Instruction set
* Set/reset/test/Boolean operation for bit data * 4-bit data transfer, arithmetic/logical, addition/subtraction and comparison * 8-bit data transfer, arithmetic/logical, addition/subtraction and comparison 2.7 to 6.0 V 4.75 to 5.5 V
Operating supply voltage Package
* 80-pin plastic QFP * 80-pin ceramic LCC with a windowNote 2
Notes 1. 2.
No mask option is provided for the PD75P516 and PD75P518. Only in the PD75P516 and PD75P518
176
PD75517(A)
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for developing a system which employs the PD75517(A). Language processor
RA75X relocatable assembler Host machine PC-9800 series Part number OS MS-DOSTM Ver. 3.10 to Ver. 3.30C PC DOSTM (Ver. 3.1) Distribution media 3.5-inch 2HD
S5A13RA75X S5A10RA75X S7B10RA75X
5-inch 2HD 5-inch 2HC
IBM PC series
PROM programming tools
Hardware PG-1500 The PG-1500 PROM programmer is used together with an accessory board and optional program adapter. It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine. The PG-1500 can be used to program typical 256K-bit to 1M-bit PROMs. The PA-75P516GF is a dedicated PROM programmer for the PD75P516GF and PD75P518GF. This programmer is connected to the PG-1500. The PA-75P516K is a dedicated PROM programmer for the PD75P516K and PD75P518K. This programmer is connected to the PG-1500. This program enables the host machine to control the PG-1500 through the serial and parallel interfaces.
PA-75P516GF
PA-75P516K Software
PG-1500 controller
Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C IBM PC series PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD 5-inch 2HD
Part number
S5A13PG1500 S5A10PG1500 S7B10PG1500
5-inch 2HC
177
PD75517(A)
Debugging tools
Hardware
IE-75000-RNote
The IE-75000-R is an in-circuit emulator available for the 75X series. This emulator is used together with the emulation probe to develop application systems of the PD75517(A). For efficient debugging, the emulator is connected to the host machine and PROM programmer. The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001R. The IE-75000-R contains the emulation board. The emulation board is used together with the IE-75000-R or IE-75001-R to evaluate the PD75517(A). The IE-75001-R is an in-circuit emulator available for the 75X series. This emulator is used together with the IE-75000-R-EM emulation board (option) and emulation probe to develop application systems of the PD75517(A). For efficient debugging, the emulator is connected to the host machine and PROM programmer. The EP-75516GF-R is an emulation probe for the PD755xx series. The emulation probe is connected to the IE-75000-R or IE-75001-R when it is used. A 80-pin conversion socket, the EV-9200G-80, attached to the probe facilitates the connection of the prove with the user system. This program enables the host machine to control the IE-75000-R or IE75001-R through the RS-232-C interface.
IE-75000-R-EM
IE-75001-R
EP-75516GF-R
EV-9200G-80 Software IE control program
Host machine OS PC-9800 series MS-DOS Ver. 3.10 to Ver. 3.30C IBM PC series PC DOS (Ver. 3.1) Distribution media 3.5-inch 2HD
Part number
S5A13IE75X S5A10IE75X S7B10IE75X
5-inch 2HD 5-inch 2HC
Note
Maintenance service only NEC is not responsible for the operation of any software unless it runs on a host machine with the operating system listed above.
Remark
178
Development tool configuration
In-circuit emulator Emulation probe IE-75000-R IE-75001-RNote 1 RS-232-C IE-75000-R-EM IE control program Host machine PC-9800 series IBM PC series (Symbolic debugging is possible.) 80-pin conversion socket EV-9200G-80 User sysytem
Centronics interface
EP-75516GF-R
PG-1500 controller PROM programmer
Built-in PROM
PD75P518GF (one-time) PD75P518K (with window)
PG-1500
Relocatable assembler
Programmer adapter PA-75P516GFNote 2 PA-75P516KNote 3
Notes 1. The IE-75001-R does not contain the IE-75000-R-EM (to be ordered). 2. For the PD75P518GF (one-time) 3. For the PD75P518K (with window)
PD75517(A)
179
PD75517(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOSTM is a trademark of Microsoft Corporation. PC DOSTM is a trademark of IBM Corporation.

▲Up To Search▲

Price & Availability of UPD75517

	To Download UPD75517 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .